EPC144ILC20 vs EPC1LC20-W Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPC144ILC20 sa pamamagitan ng Intel at EPC1LC20-W sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPC144ILC20 | EPC1LC20-W |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | Memory ICs | Memory ICs |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Manufacturer | Altera (now Intel) | — |
| Part Family | EPC144 - Configuration EPROM | — |
| Uri ng Memory | OTP CMOS Configuration EPROM (UV-erasable, factory OTP-programmed) | OTP (One-Time Programmable) Configuration PROM |
| Laki ng Memory | 440,800 bit (54 KB) | 1 Mbit |
| Interface | Serial (Altera FLEX/MAX configuration - DCLK / DATA0 / nCONFIG / nSTATUS) | Altera serial configuration (DCLK / DATA / nCONFIG / nSTATUS) |
| Supply Voltage VCC | 5 V (nominal) | — |
| Packhaging | PLCC-20 (Plastic Leaded Chip Carrier, JEDEC MS-018) | 20-PLCC J-lead (9x9 mm) |
| Hanay ng Temperature na Operasyon | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature range] |
| Configuration Mode | Master Serial / daisy-chain JTAG-style | — |
| Programmability | One-Time-Programmable (factory programmed by Altera with user bitstream) | — |
| JTAG Support | Yes (TDI/TDO pins for ByteBlasterMV / USB-Blaster ISP) | — |
| Compatible FPGAs | Altera EPF8282, EPF8452, EPF10K-series Classic FPGAs | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance] | Compliant (Pb-free -W finish) |
| Lead-Free Status | [DATA_NEEDED: lead-free status] | — |
| Uri ng Pagpapasok | Surface Mount (PLCC-20 socket or SMT land pattern) | Surface Mount (PLCC socket or direct solder) |
| Level ng MSL | [DATA_NEEDED: MSL rating] | — |
| Configuration Clock (DCLK) | — | 8 MHz maximum |
| Volte ng Pagbibigay | — | 3.3 V and 5.0 V |
| In-System Programming | — | Yes - IEEE 1149.1 (JTAG) ISP at 3.3 V / 5.0 V |
| Lead Finish | — | Pb-free (matte tin) - "-W" suffix |
| Daisy-Chain Support | — | Yes - multiple EPC1 / EPC2 devices cascade to program larger FPGAs |
| Compression Support | — | Yes - stores compressed Altera FPGA bitstreams |
| Programming Cycles | — | 1 (OTP) |
| Target FPGA Families | — | Cyclone, FLEX 6000 / 10K / 10KE, ACEX 1K, APEX 20K, Mercury |