EPC16QC100 vs EPC16QC100N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPC16QC100 sa pamamagitan ng Altera at EPC16QC100N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPC16QC100 EPC16QC100N
Brand Altera Altera
Kategorya Memory ICs Memory ICs
Katayuan ng Lifecycle Obsolete Obsolete
Uri ng Memory Flash Configuration PROM (non-volatile) —
Laki ng Memory 16 Mbit 16 Mbit (16,777,216 bits)
Configuration Clock (max) 33 MHz —
Interface Altera enhanced configuration serial interface —
In-System Programmability Yes (IEEE 1149.1 JTAG) —
Supply Voltage (VCC) 3.0 V to 3.6 V 3.0 V to 3.6 V
Temperature na Operasyon -40C to +85C (commercial) 0 C to 70 C
Packhaging 100-pin PQFP (20 x 14 mm) 100-pin PQFP (20 x 14 mm)
Uri ng Pagpapasok Surface Mount Surface Mount
Cascadable Yes (multi-device chain) —
Compression Support Yes (Altera enhanced compression) —
Supported FPGA Families Stratix, APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, Stratix II GX
Configuration Controller Integrated on-die —
Level ng MSL [DATA_NEEDED: MSL level] —
Tindminan RoHS [DATA_NEEDED: RoHS status] —
Programmable Type — In System Programmable
Configuration Clock Frequency — 33 MHz max
On-Chip Decompression — Yes (supports compressed bitstreams)
Access Time — 90 ns typical
Flash Read Bandwidth — 160 Mbps (16-bit DQ at 10 MHz)
Configuration Interface — FPP / PS / AS via dedicated FPGA pins
JTAG (IEEE 1149.1) ISP — Supported
Lead Free — Yes (per datasheet)
Packaging — Tray

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