EPC16QC100 vs EPC16QC100N 比較

詳細並排比較 EPC16QC100 由 Altera 與 EPC16QC100N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPC16QC100 EPC16QC100N
品牌 Altera Altera
類別 Memory ICs Memory ICs
生命週期狀態 Obsolete Obsolete
記憶體類型 Flash Configuration PROM (non-volatile) —
記憶體容量 16 Mbit 16 Mbit (16,777,216 bits)
Configuration Clock (max) 33 MHz —
介面 Altera enhanced configuration serial interface —
In-System Programmability Yes (IEEE 1149.1 JTAG) —
Supply Voltage (VCC) 3.0 V to 3.6 V 3.0 V to 3.6 V
工作溫度 -40C to +85C (commercial) 0 C to 70 C
封裝 100-pin PQFP (20 x 14 mm) 100-pin PQFP (20 x 14 mm)
安裝類型 Surface Mount Surface Mount
Cascadable Yes (multi-device chain) —
Compression Support Yes (Altera enhanced compression) —
Supported FPGA Families Stratix, APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, Stratix II GX
Configuration Controller Integrated on-die —
MSL 等級 [DATA_NEEDED: MSL level] —
RoHS 狀態 [DATA_NEEDED: RoHS status] —
Programmable Type — In System Programmable
Configuration Clock Frequency — 33 MHz max
On-Chip Decompression — Yes (supports compressed bitstreams)
Access Time — 90 ns typical
Flash Read Bandwidth — 160 Mbps (16-bit DQ at 10 MHz)
Configuration Interface — FPP / PS / AS via dedicated FPGA pins
JTAG (IEEE 1149.1) ISP — Supported
Lead Free — Yes (per datasheet)
Packaging — Tray

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