EPC20LI20N vs EPC2LI20N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPC20LI20N sa pamamagitan ng Intel at EPC2LI20N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPC20LI20N | EPC2LI20N |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | Memory ICs |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Uri ng Memory | EPROM (UV-erasable, in-system programmable) | Non-volatile configuration PROM (Flash) |
| Laki ng Memory | 1.6 Mbit (65,536 x 1-bit words, approx. 200 Kbyte) | 1.6 Mbit |
| Interface | Serial (4-pin Altera Passive Serial: DCLK, DATA0, nCONFIG, nSTATUS) | — |
| Volte ng Pagbibigay | 3.3 V (5.0 V compatible variant in same family) | — |
| Configuration Clock | Up to 10 MHz | — |
| Target FPGA Families | APEX II, APEX 20K/KC/KE, Mercury, ACEX 1K, FLEX 6000/10KE/10KA | — |
| Packhaging | 20-pin PLCC (9x9 mm, JEDEC MS-018) | — |
| Uri ng Pagpapasok | Surface Mount (PLCC socket or direct solder) | Surface Mount |
| Programming Interface | IEEE 1532 / JTAG (in-system) | — |
| Temperature na Operasyon | -40C to +85C (industrial) | [DATA_NEEDED: operating temperature range] |
| Standby Current | [DATA_NEEDED: standby current uA] | — |
| Active Configuration Current | [DATA_NEEDED: ICC active mA] | — |
| Programming Voltage | [DATA_NEEDED: VPP] | — |
| Programming Cycles | [DATA_NEEDED: endurance cycles] | — |
| Level ng MSL | [DATA_NEEDED: MSL rating] | — |
| Lead-Free / RoHS | [DATA_NEEDED: lead-free status] | — |
| Multi-Device Daisy-Chain | Supported via nCASC pin | — |
| Programmable Type | — | In System Programmable (ISP via JTAG) |
| Configuration Mode | — | Serial |
| Maximum Configuration Frequency | — | 10 MHz |
| Supply Voltage (VCCINT) | — | 3.0 V to 3.6 V |
| Supply Voltage (VCCIO) | — | 4.5 V to 5.5 V |
| Packhaging / Kaso | — | 20-PLCC (J-Lead), 9x9 mm |
| Packaging | — | Tube |
| Supported FPGA Series | — | ACEX 1K, APEX II, Cyclone, Stratix II |
| JTAG Interface | — | IEEE 1149.1 boundary scan (TCK/TDI/TMS/TDO) |
| Configuration Pins | — | nCS, DCLK, DATA, nCONFIG, nSTATUS, CONF_DONE |
| Tindminan RoHS | — | [DATA_NEEDED: RoHS status] |