EPC20LI20N vs EPC2LI20N 比較
詳細並排比較 EPC20LI20N 由 Intel 與 EPC2LI20N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPC20LI20N | EPC2LI20N |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | Memory ICs |
| 生命週期狀態 | NRND | Obsolete |
| 記憶體類型 | EPROM (UV-erasable, in-system programmable) | Non-volatile configuration PROM (Flash) |
| 記憶體容量 | 1.6 Mbit (65,536 x 1-bit words, approx. 200 Kbyte) | 1.6 Mbit |
| 介面 | Serial (4-pin Altera Passive Serial: DCLK, DATA0, nCONFIG, nSTATUS) | — |
| 供應電壓 | 3.3 V (5.0 V compatible variant in same family) | — |
| Configuration Clock | Up to 10 MHz | — |
| Target FPGA Families | APEX II, APEX 20K/KC/KE, Mercury, ACEX 1K, FLEX 6000/10KE/10KA | — |
| 封裝 | 20-pin PLCC (9x9 mm, JEDEC MS-018) | — |
| 安裝類型 | Surface Mount (PLCC socket or direct solder) | Surface Mount |
| Programming Interface | IEEE 1532 / JTAG (in-system) | — |
| 工作溫度 | -40C to +85C (industrial) | [DATA_NEEDED: operating temperature range] |
| Standby Current | [DATA_NEEDED: standby current uA] | — |
| Active Configuration Current | [DATA_NEEDED: ICC active mA] | — |
| Programming Voltage | [DATA_NEEDED: VPP] | — |
| Programming Cycles | [DATA_NEEDED: endurance cycles] | — |
| MSL 等級 | [DATA_NEEDED: MSL rating] | — |
| Lead-Free / RoHS | [DATA_NEEDED: lead-free status] | — |
| Multi-Device Daisy-Chain | Supported via nCASC pin | — |
| Programmable Type | — | In System Programmable (ISP via JTAG) |
| Configuration Mode | — | Serial |
| Maximum Configuration Frequency | — | 10 MHz |
| Supply Voltage (VCCINT) | — | 3.0 V to 3.6 V |
| Supply Voltage (VCCIO) | — | 4.5 V to 5.5 V |
| 封裝 / 外殼 | — | 20-PLCC (J-Lead), 9x9 mm |
| Packaging | — | Tube |
| Supported FPGA Series | — | ACEX 1K, APEX II, Cyclone, Stratix II |
| JTAG Interface | — | IEEE 1149.1 boundary scan (TCK/TDI/TMS/TDO) |
| Configuration Pins | — | nCS, DCLK, DATA, nCONFIG, nSTATUS, CONF_DONE |
| RoHS 狀態 | — | [DATA_NEEDED: RoHS status] |