EPC2L1696-10F vs EPC2L20U-HAF480119C Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPC2L1696-10F sa pamamagitan ng Altera at EPC2L20U-HAF480119C sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EPC2L20U-HAF480119C - FPGA Config Device, SRAM LUT | Intel
EPC2L20U-HAF480119C ⚠ Huling PagbiliPagsanggunian na paghahambing
| Parametro | EPC2L1696-10F | EPC2L20U-HAF480119C |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | Memory ICs | Memory ICs |
| Katayuan ng Lifecycle | NRND | Huling Pagbili |
| Device Type | Configuration EPROM for SRAM-based LUT FPGAs | — |
| Supported Logic Density | 1696 LUTs | — |
| Configuration Interface | 5-pin Altera serial (nCS, DCLK, DATA, OE, nINIT_CONF) | — |
| Memory Technology | CMOS EEPROM | — |
| Supply Voltage (VCC) | 3.3 V | — |
| Access Time | 10 ns (speed grade -10) | — |
| Maximum DCLK Frequency | [DATA_NEEDED: DCLK max frequency] | — |
| Program / Erase Cycles | >= 100,000 cycles | — |
| Data Retention | [DATA_NEEDED: data retention years] | — |
| In-System Programming | Yes (4-wire JTAG-style interface) | — |
| Temperature na Operasyon | 0C to +70C (commercial) | — |
| Packhaging | 20-pin PLCC | PLCC-20 |
| Uri ng Pagpapasok | Surface Mount | Surface Mount / Socketed |
| Level ng MSL | [DATA_NEEDED: MSL level] | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Uri ng Memory | — | Configuration PROM (non-volatile) |
| Laki ng Memory | — | 1.6 Mb |
| Target Device | — | SRAM-based LUT FPGAs (Cyclone, Stratix, APEX families) |
| Core Supply Voltage | — | 3.3 V |
| I/O Tolerance | — | 5 V tolerant |
| Configuration Modes | — | Serial (1-bit), Parallel (8-bit FPP), JTAG |
| JTAG Support | — | Yes (IEEE 1149.1 boundary-scan) |
| Programmability | — | In-system programmable via JTAG |
| Cascade Support | — | Yes (multi-PROM chains for larger FPGAs) |
| Configuration Clock Range | — | 10 MHz to 40 MHz |
| Bitstream Compression Support | — | Yes (Cyclone/Stratix compressed bitstreams) |
| Hanay ng Temperature na Operasyon | — | [DATA_NEEDED: operating temperature range] |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |