EPC2L1696-10F vs EPC2L20U-HAF480119C 比較

詳細並排比較 EPC2L1696-10F 由 Altera 與 EPC2L20U-HAF480119C 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

Intel
EPC2L20U-HAF480119C EPC2L20U-HAF480119C - FPGA Config Device, SRAM LUT | Intel

EPC2L20U-HAF480119C - FPGA Config Device, SRAM LUT | Intel

EPC2L20U-HAF480119C ⚠ 最後購買機會

規格比較

參數 EPC2L1696-10F EPC2L20U-HAF480119C
品牌 Altera Intel
類別 Memory ICs Memory ICs
生命週期狀態 NRND 最後購買
Device Type Configuration EPROM for SRAM-based LUT FPGAs —
Supported Logic Density 1696 LUTs —
Configuration Interface 5-pin Altera serial (nCS, DCLK, DATA, OE, nINIT_CONF) —
Memory Technology CMOS EEPROM —
Supply Voltage (VCC) 3.3 V —
Access Time 10 ns (speed grade -10) —
Maximum DCLK Frequency [DATA_NEEDED: DCLK max frequency] —
Program / Erase Cycles >= 100,000 cycles —
Data Retention [DATA_NEEDED: data retention years] —
In-System Programming Yes (4-wire JTAG-style interface) —
工作溫度 0C to +70C (commercial) —
封裝 20-pin PLCC PLCC-20
安裝類型 Surface Mount Surface Mount / Socketed
MSL 等級 [DATA_NEEDED: MSL level] —
RoHS 狀態 [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
記憶體類型 — Configuration PROM (non-volatile)
記憶體容量 — 1.6 Mb
Target Device — SRAM-based LUT FPGAs (Cyclone, Stratix, APEX families)
Core Supply Voltage — 3.3 V
I/O Tolerance — 5 V tolerant
Configuration Modes — Serial (1-bit), Parallel (8-bit FPP), JTAG
JTAG Support — Yes (IEEE 1149.1 boundary-scan)
Programmability — In-system programmable via JTAG
Cascade Support — Yes (multi-PROM chains for larger FPGAs)
Configuration Clock Range — 10 MHz to 40 MHz
Bitstream Compression Support — Yes (Cyclone/Stratix compressed bitstreams)
工作溫度範圍 — [DATA_NEEDED: operating temperature range]
Lead-Free — [DATA_NEEDED: lead-free status]

資料表與資源

瀏覽所有產品 建立 BOM 索取報價