EPC2L20U vs EPC2L120N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPC2L20U sa pamamagitan ng Altera at EPC2L120N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPC2L20U | EPC2L120N |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | Obsolete |
| Laki ng Memory | 1.6 Mbit | — |
| Supply Voltage (VCC) | 3.0 V to 3.6 V | — |
| Uri ng Interface | Serial configuration (DCLK/DATA0) | — |
| Programmability | In-system programmable via IEEE 1532 / JTAG | — |
| Supported FPGAs | APEX II, APEX 20K, Mercury, Stratix, Cyclone, ACEX 1K | — |
| Configuration Mode | Single + Cascade (multi-PROM daisy chain) | — |
| Compression Support | Yes (FPGA decompresses bitstream) | — |
| Temperature na Operasyon | -40C to +85C (industrial) | [DATA_NEEDED: industrial temp range] |
| Packhaging | 20-PLCC (PLCC-20) | 84-pin PLCC (J-Lead) |
| Uri ng Pagpapasok | Surface Mount / Socket | — |
| JTAG Support | Yes (IEEE Std 1149.1 boundary scan) | — |
| Bilang ng Pin | 20 | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | unknown |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Level ng MSL | [DATA_NEEDED: MSL level] | — |
| Device Type | — | Configuration Device for SRAM-based LUT FPGAs |
| Manufacturer | — | Intel (formerly Altera) |
| Family | — | EPC2 (Enhanced Configuration Device) |
| Memory Capacity | — | 165,888 bits (400,000 gates equivalent) |
| Operating Voltage (VCCIO) | — | 2.7 V to 3.6 V |
| 5V Tolerance | — | Yes (5V-tolerant I/O) |
| Configuration Clock (FPP) | — | Up to 66 MHz |
| Configuration Clock (PS) | — | Up to 33 MHz |
| Internal Oscillator | — | 8 MHz with programmable divider |
| JTAG Interface | — | IEEE Std 1149.1 compliant, ISP support |
| Programming Cycles | — | 100,000 erase/program cycles |
| Sector Erase Time | — | [DATA_NEEDED: typical sector erase time] |
| Configuration Schemes | — | FPP, PS, JTAG, daisy chain |
| Supported FPGA Families | — | Cyclone, APEX, FLEX, Mercury, ACEX, Stratix |