EPC2L20U vs EPC2L120N 比較
詳細並排比較 EPC2L20U 由 Altera 與 EPC2L120N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPC2L20U | EPC2L120N |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 最後購買 | Obsolete |
| 記憶體容量 | 1.6 Mbit | — |
| Supply Voltage (VCC) | 3.0 V to 3.6 V | — |
| 介面類型 | Serial configuration (DCLK/DATA0) | — |
| Programmability | In-system programmable via IEEE 1532 / JTAG | — |
| Supported FPGAs | APEX II, APEX 20K, Mercury, Stratix, Cyclone, ACEX 1K | — |
| Configuration Mode | Single + Cascade (multi-PROM daisy chain) | — |
| Compression Support | Yes (FPGA decompresses bitstream) | — |
| 工作溫度 | -40C to +85C (industrial) | [DATA_NEEDED: industrial temp range] |
| 封裝 | 20-PLCC (PLCC-20) | 84-pin PLCC (J-Lead) |
| 安裝類型 | Surface Mount / Socket | — |
| JTAG Support | Yes (IEEE Std 1149.1 boundary scan) | — |
| 腳位數 | 20 | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | unknown |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| MSL 等級 | [DATA_NEEDED: MSL level] | — |
| Device Type | — | Configuration Device for SRAM-based LUT FPGAs |
| Manufacturer | — | Intel (formerly Altera) |
| Family | — | EPC2 (Enhanced Configuration Device) |
| Memory Capacity | — | 165,888 bits (400,000 gates equivalent) |
| Operating Voltage (VCCIO) | — | 2.7 V to 3.6 V |
| 5V Tolerance | — | Yes (5V-tolerant I/O) |
| Configuration Clock (FPP) | — | Up to 66 MHz |
| Configuration Clock (PS) | — | Up to 33 MHz |
| Internal Oscillator | — | 8 MHz with programmable divider |
| JTAG Interface | — | IEEE Std 1149.1 compliant, ISP support |
| Programming Cycles | — | 100,000 erase/program cycles |
| Sector Erase Time | — | [DATA_NEEDED: typical sector erase time] |
| Configuration Schemes | — | FPP, PS, JTAG, daisy chain |
| Supported FPGA Families | — | Cyclone, APEX, FLEX, Mercury, ACEX, Stratix |