EPC2LC20-V vs EPC2LC20 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPC2LC20-V sa pamamagitan ng Altera at EPC2LC20 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPC2LC20-V EPC2LC20
Brand Altera Altera
Kategorya Memory ICs Memory ICs
Katayuan ng Lifecycle Obsolete NRND
Presyo ng Yunit (USD) — $7.20
Uri ng Memory Configuration PROM (Flash-based, in-system programmable) Non-volatile configuration PROM
Memory Density 1.6 Mbit —
Configuration Interface Serial (Altera FPP/PS modes via DCLK/nSTATUS/CONF_DONE) Serial (x1) to FPGA via DCLK/nCONFIG/nSTATUS/CONF_DONE
Maximum Configuration Clock 10 MHz —
Supply Voltage VCC 3.3 V 3.0 V to 3.6 V (3.3-V operation)
I/O Tolerance 5 V tolerant on configuration pins —
In-System Programming Yes, via IEEE 1149.1 JTAG (TMS/TCK/TDI/TDO) —
Cascade Support Yes, daisy-chainable for >1.6 Mbit designs Yes - daisy-chain multiple EPC2 devices via JTAG for larger bitstreams
Operating Temperature Range (V suffix) 0 °C to +70 °C (commercial) —
Package Type 20-pin PLCC (JEDEC MS-018) —
Package Dimensions 9 x 9 mm body, 1.27 mm pitch —
Uri ng Pagpapasok Surface Mount (PLCC socket compatible) Surface Mount
Supported FPGA Families APEX 20K, ACEX 1K, FLEX 10K, FLEX 6000, MAX 9000 ACEX 1K, APEX 20K/20KC/20KE, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, MAX 9000
Tindminan RoHS Compliant (per distributor listings) Non-Compliant (original Altera Pb-containing part)
Lead-Free Yes —
Laki ng Memory — 1.6 Mbit
Programming Interface — IEEE 1149.1 (JTAG) ISP, 5.0-V and 3.3-V tolerant
ISP Voltage Range — 5.0 V or 3.3 V
Packhaging — 20-pin PLCC (J-lead, 9x9 mm)
Temperature na Operasyon — -40C to +85C (industrial) [DATA_NEEDED: exact grade from datasheet]
Lead-Free Version — EPC2LC20N available as lead-free equivalent
Programming Support — Altera Programming Unit (APU), Quartus II, JTAG programmer
Boundary-Scan — IEEE 1149.1 compliant, 8-bit or 16-bit JTAG

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