EPC2LC20-V vs EPC2LC20 比較
詳細並排比較 EPC2LC20-V 由 Altera 與 EPC2LC20 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPC2LC20-V | EPC2LC20 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | Memory ICs | Memory ICs |
| 生命週期狀態 | Obsolete | NRND |
| 單價 (USD) | — | $7.20 |
| 記憶體類型 | Configuration PROM (Flash-based, in-system programmable) | Non-volatile configuration PROM |
| Memory Density | 1.6 Mbit | — |
| Configuration Interface | Serial (Altera FPP/PS modes via DCLK/nSTATUS/CONF_DONE) | Serial (x1) to FPGA via DCLK/nCONFIG/nSTATUS/CONF_DONE |
| Maximum Configuration Clock | 10 MHz | — |
| Supply Voltage VCC | 3.3 V | 3.0 V to 3.6 V (3.3-V operation) |
| I/O Tolerance | 5 V tolerant on configuration pins | — |
| In-System Programming | Yes, via IEEE 1149.1 JTAG (TMS/TCK/TDI/TDO) | — |
| Cascade Support | Yes, daisy-chainable for >1.6 Mbit designs | Yes - daisy-chain multiple EPC2 devices via JTAG for larger bitstreams |
| Operating Temperature Range (V suffix) | 0 °C to +70 °C (commercial) | — |
| Package Type | 20-pin PLCC (JEDEC MS-018) | — |
| Package Dimensions | 9 x 9 mm body, 1.27 mm pitch | — |
| 安裝類型 | Surface Mount (PLCC socket compatible) | Surface Mount |
| Supported FPGA Families | APEX 20K, ACEX 1K, FLEX 10K, FLEX 6000, MAX 9000 | ACEX 1K, APEX 20K/20KC/20KE, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, MAX 9000 |
| RoHS 狀態 | Compliant (per distributor listings) | Non-Compliant (original Altera Pb-containing part) |
| Lead-Free | Yes | — |
| 記憶體容量 | — | 1.6 Mbit |
| Programming Interface | — | IEEE 1149.1 (JTAG) ISP, 5.0-V and 3.3-V tolerant |
| ISP Voltage Range | — | 5.0 V or 3.3 V |
| 封裝 | — | 20-pin PLCC (J-lead, 9x9 mm) |
| 工作溫度 | — | -40C to +85C (industrial) [DATA_NEEDED: exact grade from datasheet] |
| Lead-Free Version | — | EPC2LC20N available as lead-free equivalent |
| Programming Support | — | Altera Programming Unit (APU), Quartus II, JTAG programmer |
| Boundary-Scan | — | IEEE 1149.1 compliant, 8-bit or 16-bit JTAG |