EPC2LI20U vs EPC1441LI20 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPC2LI20U sa pamamagitan ng Altera at EPC1441LI20 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPC2LI20U | EPC1441LI20 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | Memory ICs | Memory ICs |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Uri ng Memory | Configuration PROM (serial EEPROM) | OTP Configuration PROM (PROM) |
| Laki ng Memory | 1.6 Mbit (65,536 x 1-bit device) | — |
| Supply Voltage (VCC) | 3.0 V to 5.5 V (5.0 V nominal) | — |
| Programming Voltage | 5.0 V (via internal charge pump) | — |
| Configuration Interface | Serial 4-pin (DATA, DCLK, nCS, OE) | Altera 4-pin serial (DATA, DCLK, nCONFIG, nSTATUS) |
| Maximum DCLK Frequency | 33 MHz (fast mode) | — |
| Hanay ng Temperature na Operasyon | -40 C to +85 C (industrial) | — |
| Packhaging | 20-pin PLCC (9x9 mm) | 20-pin PLCC (J-lead, 9x9 mm) |
| Uri ng Pagpapasok | Surface Mount (PLCC socket) | — |
| Programmability | In-system programmable via JTAG (IEEE 1149.1) | — |
| Cascade Support | Yes (via nCASC pin) | — |
| Device ID | 32-bit JTAG-readable | — |
| Supported FPGA Families | APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 6000/10KE/10KA | ACEX, APEX 20K / 20KC / 20KE, FLEX 10KE, FLEX 10KA, Mercury |
| Tindminan RoHS | [DATA_NEEDED: rohs status] | [DATA_NEEDED: RoHS compliance status] |
| Level ng MSL | [DATA_NEEDED: MSL moisture sensitivity level] | [DATA_NEEDED: MSL rating] |
| Density | — | 441 kbits (440,800 bits) |
| Number of Words | — | 440,800 |
| Bits per Word | — | 1 bit |
| Volte ng Pagbibigay | — | 3.3 V |
| Temperature na Operasyon | — | -40 C to +85 C (industrial) |
| Pin Pitch | — | 1.27 mm |
| Programming Method | — | One-Time-Programmable via Altera programming hardware |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| Configuration Time | — | Depends on FPGA bitstream length and DCLK frequency |