EPC4Q100T vs EPC4QI100N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPC4Q100T sa pamamagitan ng Intel at EPC4QI100N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPC4Q100T EPC4QI100N
Brand Intel Altera
Kategorya FPGA & CPLD Memory ICs
Katayuan ng Lifecycle NRND Aktibo
Presyo ng Yunit (USD) — $10.40
Laki ng Memory 4 Mbit 4 Mbit (4,194,304 bits)
Uri ng Memory Flash (non-volatile) In-System Programmable Configuration PROM (NOR flash)
Fungsi Enhanced Configuration Device for SRAM-based LUT FPGAs —
Configuration Modes Supported PS, FPP (16-bit), AS —
Flash Access Time 90 ns (approx 10 MHz core clock) —
Maximum Configuration Data Rate 160 Mbps (FPP, 16-bit bus) —
Width ng Data Bus 16-bit (DQ[15:0]) —
In-System Programming Yes (JTAG IEEE 1149.1) —
Supply Voltage (Core) 3.3 V —
I/O Voltage Tolerance 3.3 V (5 V tolerant on legacy interface pins) —
Package Type PQFP-100 (Plastic Quad Flat Pack) —
Package Dimensions 20 x 14 mm —
Hanay ng Temperature na Operasyon [DATA_NEEDED: operating temperature range] —
Compatible FPGA Families Stratix, Cyclone, APEX, Mercury, ACEX —
Tindminan RoHS [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS compliance]
Manufacturer Intel (formerly Altera) —
Programmable Type — In System Programmable (ISP via JTAG)
Supply Voltage (VCC) — 3.0 V to 3.6 V
Interface — Altera serial (x1) configuration + JTAG
Configuration Clock DCLK — [DATA_NEEDED: DCLK maximum frequency]
Active Supply Current (ICC active) — [DATA_NEEDED: ICC active typical value]
Standby Supply Current — [DATA_NEEDED: ICC standby typical value]
Temperature na Operasyon — -40C to +85C (industrial)
Storage Temperature — -65C to +150C
Packhaging — 100-pin PQFP (PowerPQFP, 20x14 mm)
Package Code — QI100 (PQFP-100, industrial)
Uri ng Pagpapasok — Surface Mount
Level ng MSL — [DATA_NEEDED: MSL rating]
JTAG Standard — IEEE 1149.1 boundary-scan / ISP
Cascading — Supported (multi-device daisy chain)
Target FPGAs — Altera Cyclone, Cyclone II, Stratix series

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