EPC4QC1C00N vs EPC4Q100N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPC4QC1C00N sa pamamagitan ng Altera at EPC4Q100N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPC4QC1C00N EPC4Q100N
Brand Altera Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete NRND
Device Family Enhanced Configuration Device (EPC4) —
Memory Density 4 Mbit (4,194,304 bits) —
Supply Voltage (VCC) 3.0 V to 3.6 V (3.3 V typical) —
I/O Voltage Tolerance 3.3 V / 5 V tolerant —
Interface to FPGA Serial DATA, DCLK, nCONFIG, nSTATUS, CONF_DONE —
Configuration Data Width 4-bit multiplexed on single DATA pin —
Packhaging 100-pin PQFP (QFP-100) 100-pin PQFP
Temperature na Operasyon -40 C to +85 C (industrial) -40 C to +85 C (industrial)
In-System Programming JTAG (IEEE 1149.1) —
Programming Voltage On-chip generated, no external VPP —
Page Mode Yes, multi-page storage supported —
Target FPGA Families Stratix, Cyclone, APEX, Mercury, ACEX Cyclone, Stratix, APEX, Mercury, ACEX
Configuration Clock (DCLK) [DATA_NEEDED: DCLK max frequency] —
Level ng MSL 3 (per JEDEC J-STD-020) [DATA_NEEDED: per JEDEC J-STD-020]
Tindminan RoHS [DATA_NEEDED: RoHS compliance status] —
Lead-Free [DATA_NEEDED: lead-free status] —
Uri ng Memory — Flash (NOR, Enhanced Configuration Device)
Laki ng Memory — 4 Mbit (512 Kbyte)
Configuration Interface — Serial (FLEX) / Parallel / JTAG ISP
Volte ng Pagbibigay — 3.3 V
Program/Erase Cycles — [DATA_NEEDED: minimum endurance in cycles]
Uri ng Pagpapasok — Surface Mount
JTAG Support — IEEE 1149.1 compliant
In-System Programmable — Yes
Data Width (parallel mode) — 8-bit
Lead-Free / RoHS — [DATA_NEEDED: per lot]
Status — Not Recommended for New Designs (NRND)
Configuration Schemes — Active Serial (AS) / Active Parallel (AP) / Passive Serial (PS)

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