EPC4QC1C00N vs EPC4Q100N 比較
詳細並排比較 EPC4QC1C00N 由 Altera 與 EPC4Q100N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPC4QC1C00N | EPC4Q100N |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | NRND |
| Device Family | Enhanced Configuration Device (EPC4) | — |
| Memory Density | 4 Mbit (4,194,304 bits) | — |
| Supply Voltage (VCC) | 3.0 V to 3.6 V (3.3 V typical) | — |
| I/O Voltage Tolerance | 3.3 V / 5 V tolerant | — |
| Interface to FPGA | Serial DATA, DCLK, nCONFIG, nSTATUS, CONF_DONE | — |
| Configuration Data Width | 4-bit multiplexed on single DATA pin | — |
| 封裝 | 100-pin PQFP (QFP-100) | 100-pin PQFP |
| 工作溫度 | -40 C to +85 C (industrial) | -40 C to +85 C (industrial) |
| In-System Programming | JTAG (IEEE 1149.1) | — |
| Programming Voltage | On-chip generated, no external VPP | — |
| Page Mode | Yes, multi-page storage supported | — |
| Target FPGA Families | Stratix, Cyclone, APEX, Mercury, ACEX | Cyclone, Stratix, APEX, Mercury, ACEX |
| Configuration Clock (DCLK) | [DATA_NEEDED: DCLK max frequency] | — |
| MSL 等級 | 3 (per JEDEC J-STD-020) | [DATA_NEEDED: per JEDEC J-STD-020] |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance status] | — |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| 記憶體類型 | — | Flash (NOR, Enhanced Configuration Device) |
| 記憶體容量 | — | 4 Mbit (512 Kbyte) |
| Configuration Interface | — | Serial (FLEX) / Parallel / JTAG ISP |
| 供應電壓 | — | 3.3 V |
| Program/Erase Cycles | — | [DATA_NEEDED: minimum endurance in cycles] |
| 安裝類型 | — | Surface Mount |
| JTAG Support | — | IEEE 1149.1 compliant |
| In-System Programmable | — | Yes |
| Data Width (parallel mode) | — | 8-bit |
| Lead-Free / RoHS | — | [DATA_NEEDED: per lot] |
| Status | — | Not Recommended for New Designs (NRND) |
| Configuration Schemes | — | Active Serial (AS) / Active Parallel (AP) / Passive Serial (PS) |