EPC4QI100N vs EPC8QI100 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPC4QI100N sa pamamagitan ng Altera at EPC8QI100 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPC4QI100N - 4Mb In-System Programmable FPGA Config PROM | Altera (Intel)
EPC4QI100N ✓ Nakahanda
Pagsanggunian na paghahambing
| Parametro | EPC4QI100N | EPC8QI100 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | Memory ICs | Memory ICs |
| Katayuan ng Lifecycle | Aktibo | Obsolete |
| Presyo ng Yunit (USD) | $10.40 | — |
| Uri ng Memory | In-System Programmable Configuration PROM (NOR flash) | Flash (NOR, Enhanced Configuration PROM) |
| Laki ng Memory | 4 Mbit (4,194,304 bits) | 8 Mbit |
| Programmable Type | In System Programmable (ISP via JTAG) | — |
| Supply Voltage (VCC) | 3.0 V to 3.6 V | — |
| Interface | Altera serial (x1) configuration + JTAG | Altera FPGA configuration serial/parallel (FPP) + JTAG (IEEE 1149.1) |
| Configuration Clock DCLK | [DATA_NEEDED: DCLK maximum frequency] | — |
| Active Supply Current (ICC active) | [DATA_NEEDED: ICC active typical value] | — |
| Standby Supply Current | [DATA_NEEDED: ICC standby typical value] | — |
| Temperature na Operasyon | -40C to +85C (industrial) | -40C to +85C (industrial) |
| Storage Temperature | -65C to +150C | — |
| Packhaging | 100-pin PQFP (PowerPQFP, 20x14 mm) | 100-PQFP (20 x 14 mm) |
| Package Code | QI100 (PQFP-100, industrial) | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Level ng MSL | [DATA_NEEDED: MSL rating] | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance] | Non-compliant (legacy PQFP, lead-bearing) |
| JTAG Standard | IEEE 1149.1 boundary-scan / ISP | — |
| Cascading | Supported (multi-device daisy chain) | — |
| Target FPGAs | Altera Cyclone, Cyclone II, Stratix series | — |
| Supply Voltage (Core) | — | 3.3 V |
| Supply Voltage (I/O) | — | 3.3 V |
| In-System Programmability | — | IEEE Std. 1532 compliant |
| Programming Language | — | Jam STAPL |
| Boundary Scan | — | JTAG boundary-scan test supported |
| Data Compression | — | Yes (increases effective capacity) |
| Configuration Controller | — | On-chip, dedicated to Altera FPGAs |
| Initiate-Configuration Pin | — | nINIT_CONF (private JTAG instruction) |
| Compatible FPGAs | — | Stratix, Stratix II, APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K, Cyclone, Cyclone II, Arria GX, Stratix GX, Stratix II GX |