EPC4QI100N vs EPC8QI100 比較

詳細並排比較 EPC4QI100N 由 Altera 與 EPC8QI100 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPC4QI100N EPC8QI100
品牌 Altera Intel
類別 Memory ICs Memory ICs
生命週期狀態 啟用中 Obsolete
單價 (USD) $10.40 —
記憶體類型 In-System Programmable Configuration PROM (NOR flash) Flash (NOR, Enhanced Configuration PROM)
記憶體容量 4 Mbit (4,194,304 bits) 8 Mbit
Programmable Type In System Programmable (ISP via JTAG) —
Supply Voltage (VCC) 3.0 V to 3.6 V —
介面 Altera serial (x1) configuration + JTAG Altera FPGA configuration serial/parallel (FPP) + JTAG (IEEE 1149.1)
Configuration Clock DCLK [DATA_NEEDED: DCLK maximum frequency] —
Active Supply Current (ICC active) [DATA_NEEDED: ICC active typical value] —
Standby Supply Current [DATA_NEEDED: ICC standby typical value] —
工作溫度 -40C to +85C (industrial) -40C to +85C (industrial)
Storage Temperature -65C to +150C —
封裝 100-pin PQFP (PowerPQFP, 20x14 mm) 100-PQFP (20 x 14 mm)
Package Code QI100 (PQFP-100, industrial) —
安裝類型 Surface Mount Surface Mount
MSL 等級 [DATA_NEEDED: MSL rating] —
RoHS 狀態 [DATA_NEEDED: RoHS compliance] Non-compliant (legacy PQFP, lead-bearing)
JTAG Standard IEEE 1149.1 boundary-scan / ISP —
Cascading Supported (multi-device daisy chain) —
Target FPGAs Altera Cyclone, Cyclone II, Stratix series —
Supply Voltage (Core) — 3.3 V
Supply Voltage (I/O) — 3.3 V
In-System Programmability — IEEE Std. 1532 compliant
Programming Language — Jam STAPL
Boundary Scan — JTAG boundary-scan test supported
Data Compression — Yes (increases effective capacity)
Configuration Controller — On-chip, dedicated to Altera FPGAs
Initiate-Configuration Pin — nINIT_CONF (private JTAG instruction)
Compatible FPGAs — Stratix, Stratix II, APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K, Cyclone, Cyclone II, Arria GX, Stratix GX, Stratix II GX

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