EPC8QI100N vs EPC4QI100N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPC8QI100N sa pamamagitan ng Altera at EPC4QI100N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPC8QI100N EPC4QI100N
Brand Altera Altera
Kategorya EEPROM Memory ICs
Katayuan ng Lifecycle NRND Aktibo
Presyo ng Yunit (USD) — $10.40
Manufacturer Altera (Intel) —
Part Family EPC8 (Enhanced Configuration) —
Device Type Configuration PROM for SRAM-based FPGAs —
Laki ng Memory 8 Mbit (8,388,608 bits) 4 Mbit (4,194,304 bits)
Programmable Type In System Programmable (Flash) In System Programmable (ISP via JTAG)
Configuration Interface Altera serial (4-wire: DATA, DCLK, nCS, nINIT_CONF) —
Maximum Configuration Clock 50 MHz —
On-Chip Decompression Yes (Altera compression algorithm) —
Supply Voltage (VCC) 3.0 V to 3.6 V 3.0 V to 3.6 V
Temperature na Operasyon -40 °C to +85 °C (Industrial) -40C to +85C (industrial)
Packhaging 100-PQFP / 100-BQFP (20 x 14 mm) 100-pin PQFP (PowerPQFP, 20x14 mm)
Bilang ng Pin 100 —
Uri ng Pagpapasok Surface Mount Surface Mount
Lead-Free / RoHS Yes (per distributor listings) —
JTAG (IEEE 1149.1) ISP Supported —
Multi-Device Daisy-Chain Supported —
Target FPGA Families ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, Stratix II GX —
Packaging Tray —
Uri ng Memory — In-System Programmable Configuration PROM (NOR flash)
Interface — Altera serial (x1) configuration + JTAG
Configuration Clock DCLK — [DATA_NEEDED: DCLK maximum frequency]
Active Supply Current (ICC active) — [DATA_NEEDED: ICC active typical value]
Standby Supply Current — [DATA_NEEDED: ICC standby typical value]
Storage Temperature — -65C to +150C
Package Code — QI100 (PQFP-100, industrial)
Level ng MSL — [DATA_NEEDED: MSL rating]
Tindminan RoHS — [DATA_NEEDED: RoHS compliance]
JTAG Standard — IEEE 1149.1 boundary-scan / ISP
Cascading — Supported (multi-device daisy chain)
Target FPGAs — Altera Cyclone, Cyclone II, Stratix series

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