EPF10K250EFC672-2 vs EPF10K250EFI672-3 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPF10K250EFC672-2 sa pamamagitan ng Intel at EPF10K250EFI672-3 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPF10K250EFC672-2 | EPF10K250EFI672-3 |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | NRND |
| Family | FLEX 10KE | FLEX 10KE |
| Logic Elements | 12,480 | [DATA_NEEDED: exact LE count] |
| Typical Gates | 250,000 | 250,000 |
| Embedded Array Blocks (EABs) | 20 | 12 |
| Maximum User RAM Bits | 40,960 | — |
| User I/Os | 470 | — |
| Packhaging | 672-BGA (FineLine BGA), 45 x 45 mm, 1.27 mm pitch | 672-ball FineLine BGA, 1.27 mm pitch |
| Bilang ng Pin | 672 | — |
| Propagation Delay | 0.4 ns | — |
| Temperature na Operasyon | 0 C to +70 C (Commercial) | 0 °C to 70 °C (commercial) |
| Core Supply Voltage | 2.3 V (typical 2.5 V) | 2.5 V |
| I/O Standard Support | 1.8 V, 2.5 V, 3.3 V (multi-volt I/O) | — |
| Logic Family | CMOS, SRAM-based | — |
| Configuration | SRAM, in-system programmable (ISP) via JTAG | — |
| Boundary Scan | IEEE 1149.1 (JTAG) compliant | — |
| Uri ng Pagpapasok | Surface Mount | — |
| Tindminan RoHS | Non-RoHS Compliant (per Fly-Wing listing) | Unknown (legacy Altera non-RoHS device) |
| User I/O Pins | — | 470 |
| EAB Dual-Port Width | — | Up to 16-bit |
| Maximum EAB Memory | — | [DATA_NEEDED: bits per EAB] |
| Propagation Delay (tpd) | — | 0.4 ns (typical, -3 speed grade) |
| I/O Supply Voltage | — | 2.5 V / 3.3 V (multiVolt I/O) |
| Process Technology | — | CMOS, SRAM-based configuration |
| Configuration Interface | — | JTAG / ByteBlaster (EPC2/EPC8 PROM) |
| Design Entry | — | EDIF 2 0 0 / 3 0 0, LPM, VHDL, Verilog |