EPM240ZM100C7N vs 5M240ZM68I5N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM240ZM100C7N sa pamamagitan ng Altera at 5M240ZM68I5N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPM240ZM100C7N - MAX II Z CPLD 192MC 7.5ns 100-MBGA | Altera/Intel
EPM240ZM100C7N ✓ Nakahanda
Pagsanggunian na paghahambing
| Parametro | EPM240ZM100C7N | 5M240ZM68I5N |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Family | MAX II Z | — |
| Series | MAX II | MAX V |
| Logic Elements | 240 | 240 |
| Macrocells | 192 | — |
| Pin-to-Pin Logic Delay (tPD) | 7.5 ns | — |
| User I/Os | 80 | — |
| User Flash Memory (UFM) | 8 Kbits | — |
| Core Supply Voltage (VCCINT) | 1.8 V | — |
| I/O Supply Voltage (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt) | — |
| Packhaging | 100-MBGA (Micro FineLine BGA), 6 x 6 mm | — |
| Configuration Memory | On-chip non-volatile flash | Nonvolatile Flash |
| Process Technology | 0.18 µm 6-layer-metal flash | — |
| JTAG Support | IEEE 1149.1 (programming + boundary-scan) | — |
| Temperature na Operasyon | 0 °C to +85 °C (commercial) | — |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount |
| Lead-Free / RoHS | Compliant per datasheet | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Number of Macrocells | — | 192 |
| Propagation Delay (tPD) | — | 7.5 ns |
| Package Type | — | TFBGA-68 |
| Number of Terminals | — | 68 (ball) |
| Package Code | — | TFBGA |
| Form of Terminal | — | Ball |
| Package Shape | — | Square |
| Operating Temperature Grade | — | Industrial |
| JTAG Interface | — | TMS, TDI, TDO, TCK (Bank 1) |
| Programming Method | — | JTAG / in-system programmable |
| Volte ng Pagbibigay | — | [DATA_NEEDED: VCCINT and VCCIO levels] |
| I/O Standards | — | Multiple (LVTTL, LVCMOS, SSTL, etc., per MAX V doc; PCI and 1.2 V LVCMOS excluded for JTAG pins) |
| Tindminan RoHS | — | Compliant |
| Lead Free | — | Yes |