EPM3064AT100-10N vs EPM3064ATC100-10NA Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM3064AT100-10N sa pamamagitan ng Altera at EPM3064ATC100-10NA sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM3064AT100-10N EPM3064ATC100-10NA
Brand Altera Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND Aktibo
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Macrocells 64 64
Logic Array Blocks (LABs) 4 4
Usable Gates 1,250 1,250
User I/O Pins 66 —
Speed Grade -10 (10 ns pin-to-pin delay) —
Supply Voltage (VCCINT) 3.3 V 3.3 V
I/O Bank Voltage 3.3 V —
5 V Tolerant Inputs Yes (via clamping diodes) —
Configuration Memory EEPROM (non-volatile) Non-volatile EEPROM
Programming Interface JTAG (IEEE Std. 1149.1) with pin-locking —
ISP Compliance IEEE Std. 1532 —
Boundary-Scan Test (BST) IEEE Std. 1149.1 compliant —
Packhaging TQFP-100 (T100), 14 mm x 14 mm TQFP-100 (0.5 mm pitch)
Operating Temperature (Commercial) 0C to +70C —
Tindminan RoHS [DATA_NEEDED: RoHS compliance status] —
Lead-Free [DATA_NEEDED: lead-free finish] —
User I/Os — 66
Pin-to-Pin Delay (tPD) — 10 ns
Maximum Operating Frequency — [DATA_NEEDED: fMAX in MHz]
MultiVolt I/O Voltages — 2.5 V / 3.3 V / 5.0 V
In-System Programming — IEEE Std. 1532 compliant
Boundary-Scan Test — IEEE Std. 1149.1 (JTAG)
Temperature na Operasyon — 0C to +70C (commercial)
Lead-Free / RoHS — Yes (NA suffix)

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