EPM3064ATC-100-10N vs EPM3064ATC100-10 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM3064ATC-100-10N sa pamamagitan ng Altera at EPM3064ATC100-10 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Altera
EPM3064ATC-100-10N EPM3064ATC-100-10N - 64-Macrocell MAX 3000A CPLD, 10ns | Altera

EPM3064ATC-100-10N - 64-Macrocell MAX 3000A CPLD, 10ns | Altera

EPM3064ATC-100-10N ✓ Nakahanda

Pagsanggunian na paghahambing

Parametro EPM3064ATC-100-10N EPM3064ATC100-10
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Aktibo NRND
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) —
Macro Cells 64 —
Logic Array Blocks (LABs) 2 —
User I/O Pins 66 34
Usable Gates (min) 600 —
Usable Gates (typical) 1,250 —
Pin-to-Pin Delay (tPD) 10 ns —
Counter Frequency (fCNT) 227.3 MHz —
Supply Voltage (VCCINT) 3.3 V 3.3 V
In-System Programmability Yes (IEEE 1532 / JTAG 1149.1) IEEE Std. 1149.1 (JTAG) and IEEE Std. 1532 compliant
Programming Interface 4-pin JTAG (TCK/TMS/TDI/TDO) —
Packhaging TQFP-100 TQFP-100 (100-pin Thin Quad Flat Pack)
Uri ng Pagpapasok Surface Mount —
Temperature na Operasyon 0C to +70C (commercial) —
Tindminan RoHS Compliant [DATA_NEEDED: RoHS compliance]
Logic Gates — 1250 gates
Macrocells — 64
Logic Array Blocks — 2
Propagation Delay (tPD) — 10 ns
Process Technology — CMOS EEPROM
Global Clock Signals — 2 (with optional inversion)
Output Enable Signals — 6 or 10 pin- or logic-driven
Output Slew-Rate Control — Programmable
Operating Temperature Grade — Commercial
MultiVolt I/O Support — 1.5V / 1.8V / 2.5V / 3.3V interfaces

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