EPM3064ATI44-7N vs EPM3064ATC44-7N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM3064ATI44-7N sa pamamagitan ng Altera at EPM3064ATC44-7N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM3064ATI44-7N EPM3064ATC44-7N
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND Obsolete
Family MAX 3000A MAX 3000A
Logic Elements / Macrocells 64 macrocells —
Usable Gates 1,250 gates 1,250
Maximum Frequency (fMAX) 135.1 MHz —
Pin-to-Pin Logic Delay 7 ns (speed grade -7) —
User I/O Count 34 I/O —
Dedicated Input Pins 4 —
Supply Voltage (VCCINT) 3.3 V —
I/O Bank Voltage (VCCIO) 1.8 V / 2.5 V / 3.3 V / 5 V tolerant (multiVolt) —
Program Memory Type EEPROM (in-system programmable) —
Programming Interface IEEE 1149.1 JTAG —
Packhaging 44-pin TQFP (10x10 mm, 0.8 mm pitch) 44-pin TQFP
Operating Temperature Grade Industrial (-40C to +85C) —
Tindminan RoHS Compliant (lead-free, 'N' suffix) Compliant
Process Technology 0.30 µm CMOS EEPROM —
Device Type — CPLD (Complex Programmable Logic Device)
Macro Cells — 64
Logic Array Blocks — 2
User I/O Pins — 34
Bilang ng Pins — 44
Speed Grade — -7 (7.5 ns pin-to-pin delay)
Pin-to-Pin Delay (tPD) — 7.5 ns
Maximum Counter Frequency — 192.3 MHz (-7 grade)
Supply Voltage (VCC) — 3.3 V
MultiVolt I/O — 1.8 V / 2.5 V / 3.3 V
Programmability — EEPROM, in-system programmable (ISP)
JTAG Interface — IEEE Std. 1149.1 compliant
ISP Standard — IEEE Std. 1532 compliant
Boundary-Scan Test (BST) — Built-in, JTAG-driven
Temperature na Operasyon — 0°C to +85°C (commercial)
Uri ng Pagpapasok — Surface Mount

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