EPM3128AFI256-10N vs EPM3128ATC100-10NS Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM3128AFI256-10N sa pamamagitan ng Altera at EPM3128ATC100-10NS sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM3128AFI256-10N EPM3128ATC100-10NS
Brand Altera Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Aktibo Obsolete
Family MAX 3000A MAX 3000A
Logic Density 2.5K gates —
Macro Cells 128 128
User I/Os 98 80
Speed Grade -10 (10 ns pin-to-pin) —
Propagation Delay (tPD) 10 ns —
Counter Frequency (max) 227.3 MHz —
Logic Family CMOS, EEPROM-based —
Supply Voltage (Core) 3.3 V —
I/O Compatibility 5.0 V, 3.3 V, 2.5 V (MultiVolt) —
In-System Programmability Yes (JTAG / IEEE 1149.1) —
Packhaging 256-ball FineLine BGA (FBGA-256) TQFP-100
Temperature na Operasyon -40C to +85C (industrial, per 'I' suffix) [DATA_NEEDED: operating temperature range]
Bilang ng Pin 256 100
Tindminan RoHS Compliant [DATA_NEEDED: RoHS compliance status]
Configuration Memory EEPROM (non-volatile) EEPROM (non-volatile)
PCI Compliance PCI Local Bus Spec Rev 2.2 —
Device Type — CPLD (Complex Programmable Logic Device)
Pin-to-Pin Logic Delay (tPD) — 10 ns
Counter Frequency (fCNT) — up to 227.3 MHz
Supply Voltage - Core (VCCINT) — 3.3 V
Supply Voltage - I/O (VCCIO) — 3.3 V or 2.5 V (5.0 V-tolerant inputs)
Logic-Level Compatibility — 5.0 V, 3.3 V, 2.5 V
Programmability — In-system (ISP), IEEE Std. 1532
Boundary Scan — IEEE 1149.1 JTAG
Uri ng Pagpapasok — Surface Mount
Lead-Free — [DATA_NEEDED: lead-free status]

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