EPM3128ATC100-5 vs EPM3128ATI100-5N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM3128ATC100-5 sa pamamagitan ng Intel at EPM3128ATI100-5N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM3128ATC100-5 EPM3128ATI100-5N
Brand Intel Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Aktibo
Series MAX 3000A —
Family CPLD - MAX 3000A MAX 3000A
Macrocells 128 128
Usable Gates 2,500 —
User I/Os 80 —
Dedicated Inputs 4 —
Pin-to-Pin Delay (tpd) 5 ns (commercial); 7.5 ns —
Maximum Frequency (fCNT) 192.3 MHz —
Supply Voltage (VCCINT/VCCIO) 3.3 V —
Output Drive Voltage 2.5 V or 3.3 V (programmable) —
Input Tolerance 2.5 V, 3.3 V, 5.0 V tolerant —
Program Memory Type EEPROM —
In-System Programmability Yes, IEEE Std. 1532 compliant —
JTAG Boundary Scan Yes, IEEE Std. 1149.1 —
Temperature na Operasyon 0 °C to 70 °C (Commercial) -40C to +85C (Industrial)
Packhaging 100-pin TQFP (Fine Line) 100-pin TQFP
Uri ng Pagpapasok Surface Mount Surface Mount
Logic Family CMOS —
Tindminan RoHS [DATA_NEEDED: RoHS status] Compliant (lead-free TQFP package)
Process Technology CMOS EEPROM —
Device Type — CPLD (Complex Programmable Logic Device)
Logic Array Blocks (LABs) — 8 (16 macrocells per LAB)
User I/O Pins — 80
Pin-to-Pin Delay (tPD) — 5.0 ns
Supply Voltage (VCCINT) — 3.3 V
I/O Standard — 3.3 V LVCMOS / LVTTL, 5.0 V tolerant inputs
Programming Method — In-System Programmable via IEEE Std. 1532 (JTAG)
Configuration Memory — Non-volatile EEPROM
JTAG Support — IEEE 1149.1 boundary scan

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