EPM3128ATC100-7 vs EPM3128ATI100-10 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM3128ATC100-7 sa pamamagitan ng Intel at EPM3128ATI100-10 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM3128ATC100-7 EPM3128ATI100-10
Brand Intel Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Aktibo
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Macro Cells 128 128
Typical Gates 2500 —
User I/Os 80 80
Logic Elements / LABs 4 Logic Array Blocks (LABs) [DATA_NEEDED: LAB count]
Propagation Delay (tPD) 7.5 ns —
Counter Frequency (fCNT) 129.9 MHz up to 227.3 MHz
Supply Voltage (VCCINT) 3.3 V 3.3 V
I/O Voltage Tolerance 5.0 V tolerant inputs —
Programming Technology EEPROM (non-volatile, in-system programmable) —
ISP Standard IEEE Std. 1532 (JTAG) —
Packhaging 100-pin TQFP, 14x14 mm, 0.5 mm pitch TQFP-100 (1.0 mm pitch, 14x14 mm)
Temperature na Operasyon 0C to +70C (Commercial) -40 °C to +85 °C (industrial)
Speed Grade -7 (fastest grade in family) —
Process Technology CMOS EEPROM CMOS EEPROM
Tindminan RoHS [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status -10 suffix historically Pb-free; -10N suffix is lead-free]
Lead-Free [DATA_NEEDED: lead-free status] —
Usable Gates — 2,500
Pin-to-Pin Delay (tPD) — 10 ns
MultiVolt I/O Levels — 5.0 V / 3.3 V / 2.5 V compatible
Programmability — EEPROM, 3.3 V in-system (JTAG)
Open-Drain Output Option — Yes (per I/O pin)
Boundary-Scan (JTAG) — IEEE 1149.1 compliant
Uri ng Pagpapasok — Surface Mount

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