EPM3256AFC256-7 vs EPM3256ATC144-7 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM3256AFC256-7 sa pamamagitan ng Altera at EPM3256ATC144-7 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM3256AFC256-7 EPM3256ATC144-7
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) —
Macro Cells 256 —
Logic Array Blocks (LABs) 16 —
Usable Gates 10,000 —
User I/Os 161 116
Pin-to-Pin Logic Delay 4.5 ns (max) —
Counter Frequency 227.3 MHz (max) —
Propagation Delay (tpd) 10 ns —
Core Voltage 3.3 V —
I/O Compatibility 5.0 V / 3.3 V / 2.5 V (MultiVolt I/O) —
Process Technology CMOS EEPROM, 0.30 µm —
In-System Programmability IEEE Std. 1532-compliant 3.3-V ISP —
Boundary-Scan Test JTAG (IEEE 1149.1) —
Packhaging FBGA-256 (FineLine BGA), 256 balls TQFP-144 (LFQFP, gull-wing)
Temperature na Operasyon 0 °C to 70 °C (Commercial) 0C to +70C (Commercial)
Speed Grade -7 -7
Tindminan RoHS [DATA_NEEDED: RoHS compliance status] —
Macrocells — 256
Logic Elements / Gates — 600 to 10,000 usable gates
Propagation Delay (tPD) — 7.5 ns
Counter Frequency (fCNT) — 227.3 MHz
Supply Voltage - Core (VCCINT) — 3.3 V
Supply Voltage - I/O (VCCIO) — 2.5 V / 3.3 V / 5.0 V
In-System Programming — IEEE Std. 1532 compliant, 3.3 V ISP
Bilang ng Pin — 144
Uri ng Pagpapasok — Surface Mount
PCI Compliance — PCI Local Bus Specification Revision 2.2 (speed grades -4 to -10)
JTAG Support — IEEE Std. 1149.1 boundary-scan

Mga Datasheets at Resources

Tingnan ang Lahat ng mga Produkto Lumikha ng BOM Hilingin ang Kita