EPM3512AFC256-18 vs EPM3512AFC256-20 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM3512AFC256-18 sa pamamagitan ng Altera at EPM3512AFC256-20 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPM3512AFC256-18 - MAX 3000A CPLD, 512 Macrocells, BGA-256 | Altera
EPM3512AFC256-18 ObsoleteAltera
EPM3512AFC256-20 - MAX 3000A CPLD, 512 Macrocells, BGA-256 | Altera
EPM3512AFC256-20 ObsoletePagsanggunian na paghahambing
| Parametro | EPM3512AFC256-18 | EPM3512AFC256-20 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | MAX 3000A | MAX 3000A |
| Macrocells | 512 | 512 |
| Logic Array Blocks (LABs) | 16 | — |
| Maximum User I/O Pins | 212 | — |
| Pin-to-Pin Delay (tPD1) | 18 ns | — |
| Global Clock Networks | 4 | — |
| VCCINT (Core Supply) | 3.0 V to 3.6 V (3.3 V typical) | — |
| VCCIO (I/O Supply) | 2.5 V or 3.3 V (MultiVolt) | — |
| Temperature na Operasyon | [DATA_NEEDED: industrial/commercial grade] | [DATA_NEEDED: operating temperature range] |
| Programming Technology | EEPROM (non-volatile) | — |
| In-System Programming | IEEE Std. 1532 / JTAG (IEEE Std. 1149.1) | — |
| Packhaging | 256-ball FineLine BGA (FCBGA) | 256-ball FBGA (Fine-pitch BGA) |
| Ball Pitch | 1.0 mm | — |
| Tindminan RoHS | [DATA_NEEDED: not specified in retrieved data] | [DATA_NEEDED: RoHS compliance status] |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Typical Usable Gates | — | 10,000 |
| Speed Grade | — | -20 (20 ns tPD) |
| Bilang ng Pin | — | 256 |
| Operating Voltage (VCCINT) | — | 3.3 V (3.0 V to 3.6 V) |
| I/O Voltage (VCCIO) | — | 2.5 V or 3.3 V (5.0 V tolerant inputs) |
| I/O Standards | — | LVTTL, LVCMOS, 2.5 V, 3.3 V, 5.0 V tolerant |
| Program Memory Type | — | EEPROM (non-volatile) |
| In-System Programmability | — | Yes (JTAG IEEE 1149.1) |
| JTAG Support | — | Yes (boundary-scan + ISP) |
| Level ng MSL | — | [DATA_NEEDED: MSL moisture sensitivity level] |
| Configuration Memory | — | Internal EEPROM |