EPM3512AFC256-2 vs EPM3512AFC256-20 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM3512AFC256-2 sa pamamagitan ng Altera at EPM3512AFC256-20 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM3512AFC256-2 EPM3512AFC256-20
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family MAX 3000A MAX 3000A
Macrocells 512 512
Logic Array Blocks (LABs) 16 —
Maximum User I/O Pins 212 —
Propagation Delay (tPD, -2 grade) [DATA_NEEDED: tPD ns] —
Maximum Operating Frequency [DATA_NEEDED: fMAX MHz] —
Core Supply Voltage 3.3 V —
I/O Output Drive Voltage 2.5 V or 3.3 V (MultiVolt) —
Input Tolerance 2.5 V, 3.3 V, 5.0 V tolerant —
Packhaging BGA-256 (FineLine BGA) 256-ball FBGA (Fine-pitch BGA)
Ball Pitch 1.0 mm —
Programming Interface JTAG (IEEE Std 1149.1) / ByteBlaster —
Process Technology 0.30 um CMOS EEPROM —
Temperature na Operasyon 0C to +70C (commercial) [DATA_NEEDED: operating temperature range]
Tindminan RoHS [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS compliance status]
Speed Grade -2 -20 (20 ns tPD)
Typical Usable Gates — 10,000
Bilang ng Pin — 256
Operating Voltage (VCCINT) — 3.3 V (3.0 V to 3.6 V)
I/O Voltage (VCCIO) — 2.5 V or 3.3 V (5.0 V tolerant inputs)
I/O Standards — LVTTL, LVCMOS, 2.5 V, 3.3 V, 5.0 V tolerant
Program Memory Type — EEPROM (non-volatile)
In-System Programmability — Yes (JTAG IEEE 1149.1)
JTAG Support — Yes (boundary-scan + ISP)
Uri ng Pagpapasok — Surface Mount
Level ng MSL — [DATA_NEEDED: MSL moisture sensitivity level]
Configuration Memory — Internal EEPROM

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