EPM3512AFC256-2 vs EPM3512AFC256-20 Comparison

Detailed side-by-side comparison of EPM3512AFC256-2 by Altera and EPM3512AFC256-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3512AFC256-2 EPM3512AFC256-20
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $14.85 $9.75
Family MAX 3000A MAX 3000A
Macrocells 512 512
Logic Array Blocks (LABs) 16 β€”
Maximum User I/O Pins 212 β€”
Propagation Delay (tPD, -2 grade) [DATA_NEEDED: tPD ns] β€”
Maximum Operating Frequency [DATA_NEEDED: fMAX MHz] β€”
Core Supply Voltage 3.3 V β€”
I/O Output Drive Voltage 2.5 V or 3.3 V (MultiVolt) β€”
Input Tolerance 2.5 V, 3.3 V, 5.0 V tolerant β€”
Package BGA-256 (FineLine BGA) 256-ball FBGA (Fine-pitch BGA)
Ball Pitch 1.0 mm β€”
Programming Interface JTAG (IEEE Std 1149.1) / ByteBlaster β€”
Process Technology 0.30 um CMOS EEPROM β€”
Operating Temperature 0C to +70C (commercial) [DATA_NEEDED: operating temperature range]
RoHS Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS compliance status]
Speed Grade -2 -20 (20 ns tPD)
Typical Usable Gates β€” 10,000
Pin Count β€” 256
Operating Voltage (VCCINT) β€” 3.3 V (3.0 V to 3.6 V)
I/O Voltage (VCCIO) β€” 2.5 V or 3.3 V (5.0 V tolerant inputs)
I/O Standards β€” LVTTL, LVCMOS, 2.5 V, 3.3 V, 5.0 V tolerant
Program Memory Type β€” EEPROM (non-volatile)
In-System Programmability β€” Yes (JTAG IEEE 1149.1)
JTAG Support β€” Yes (boundary-scan + ISP)
Mounting Type β€” Surface Mount
MSL Level β€” [DATA_NEEDED: MSL moisture sensitivity level]
Configuration Memory β€” Internal EEPROM

Datasheets & Resources

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