EPM3512AFC256-22 vs EPM3512AFC256-21 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM3512AFC256-22 sa pamamagitan ng Intel at EPM3512AFC256-21 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM3512AFC256-22 EPM3512AFC256-21
Brand Intel Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete NRND
Family MAX 3000A —
Device Type CPLD (Complex Programmable Logic Device) —
Macrocells 512 —
Logic Array Blocks (LABs) 16 16
Maximum User I/O Pins 208 (typical for FC256 package) —
Speed Grade -22 (tPD ~22 ns) —
Propagation Delay (tPD) 22 ns —
Supply Voltage VCCINT 3.3 V —
I/O Standards Supported 2.5 V, 3.3 V, 5.0 V (VCCIO selectable) —
In-System Programming IEEE Std. 1532-compliant ISP via JTAG —
Configuration Memory On-chip EEPROM (non-volatile) —
Packhaging FC-256 (FineLine BGA, 256 balls, 1.0 mm pitch) FBGA-256 (FineLine BGA)
Uri ng Pagpapasok Surface Mount (BGA) Surface Mount (BGA)
Temperature na Operasyon [DATA_NEEDED: operating temperature grade] -40C to +85C (industrial)
Tindminan RoHS [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: RoHS compliance status]
Device Family — MAX 3000A
Logic Elements / Macrocells — 512 macrocells
Usable Gates — 10,000
Maximum Operating Frequency — 87 MHz
Supply Voltage - Core (VCCINT) — 3.3 V
I/O Supply Voltage (VCCIO) — 2.5 V / 3.3 V / 5.0 V (multi-volt I/O)
Programmable Pins (max) — [DATA_NEEDED: maximum user I/O pin count]
Programming Interface — JTAG / IEEE Std. 1532 ISP
Uri ng Memory — Non-volatile EPROM/EEPROM cell array
Lead-Free — [DATA_NEEDED: lead-free status]

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