EPM3512AFC256-22 vs EPM3512AFC256-21 比較

詳細並排比較 EPM3512AFC256-22 由 Intel 與 EPM3512AFC256-21 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPM3512AFC256-22 EPM3512AFC256-21
品牌 Intel Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete NRND
Family MAX 3000A —
Device Type CPLD (Complex Programmable Logic Device) —
Macrocells 512 —
Logic Array Blocks (LABs) 16 16
Maximum User I/O Pins 208 (typical for FC256 package) —
Speed Grade -22 (tPD ~22 ns) —
Propagation Delay (tPD) 22 ns —
Supply Voltage VCCINT 3.3 V —
I/O Standards Supported 2.5 V, 3.3 V, 5.0 V (VCCIO selectable) —
In-System Programming IEEE Std. 1532-compliant ISP via JTAG —
Configuration Memory On-chip EEPROM (non-volatile) —
封裝 FC-256 (FineLine BGA, 256 balls, 1.0 mm pitch) FBGA-256 (FineLine BGA)
安裝類型 Surface Mount (BGA) Surface Mount (BGA)
工作溫度 [DATA_NEEDED: operating temperature grade] -40C to +85C (industrial)
RoHS 狀態 [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: RoHS compliance status]
Device Family — MAX 3000A
Logic Elements / Macrocells — 512 macrocells
Usable Gates — 10,000
Maximum Operating Frequency — 87 MHz
Supply Voltage - Core (VCCINT) — 3.3 V
I/O Supply Voltage (VCCIO) — 2.5 V / 3.3 V / 5.0 V (multi-volt I/O)
Programmable Pins (max) — [DATA_NEEDED: maximum user I/O pin count]
Programming Interface — JTAG / IEEE Std. 1532 ISP
記憶體類型 — Non-volatile EPROM/EEPROM cell array
Lead-Free — [DATA_NEEDED: lead-free status]

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