EPM3512AFC256-3N vs EPM3512AFC256-10N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM3512AFC256-3N sa pamamagitan ng Altera at EPM3512AFC256-10N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Altera
EPM3512AFC256-3N EPM3512AFC256-3N - MAX 3000A CPLD 512 Macrocells | Altera

EPM3512AFC256-3N - MAX 3000A CPLD 512 Macrocells | Altera

EPM3512AFC256-3N ✓ Nakahanda

Pagsanggunian na paghahambing

Parametro EPM3512AFC256-3N EPM3512AFC256-10N
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Aktibo Obsolete
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) —
Macrocells 512 512
Usable Gates 10,000 10000
Logic Array Blocks (LABs) 16 [DATA_NEEDED: number of LABs]
Maximum Operating Frequency 116.3 MHz —
Pin-to-Pin Delay (tPD) 3.5 ns (speed grade -3) 10 ns
Speed Grade -3 (slowest in family) —
Core Supply Voltage (VCCINT) 3.3 V —
I/O Supply Voltage (VCCIO) 2.5 V / 3.3 V / 5.0 V (MultiVolt) —
Packhaging 256-ball FineLine BGA (FC-256) 256-ball FBGA (17 mm x 17 mm)
Uri ng Pagpapasok Surface Mount Surface Mount (BGA)
Programming Interface JTAG (IEEE 1149.1) / IEEE Std. 1532 ISP —
Configuration Memory Non-volatile EEPROM —
Temperature na Operasyon [DATA_NEEDED: operating temperature grade] —
Tindminan RoHS [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: RoHS status]
User I/O Pins — 208
Operating Frequency (fMAX) — [DATA_NEEDED: fMAX MHz]
Setup Time (tSU) — 4.5 ns
VCCINT (Core Supply) — 3.3 V
VCCIO (I/O Supply) — 3.3 V or 2.5 V
Technology — CMOS EEPROM-based, non-volatile
Operating Temperature (Commercial) — 0 C to +70 C
ISP Interface — IEEE Std. 1149.1 JTAG, IEEE Std. 1532
Level ng MSL — [DATA_NEEDED: MSL rating]

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