EPM3512AFI256-7 vs EPM3512AFC256-7 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM3512AFI256-7 sa pamamagitan ng Altera at EPM3512AFC256-7 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM3512AFI256-7 EPM3512AFC256-7
Brand Altera Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Huling Pagbili
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Macrocells 512 512
Usable Gates 10,000 10,000
Logic Array Blocks (LABs) 32 (16 macrocells each) 16
User I/O Pins 208 212
Pin-to-Pin Delay (tPD) 7.5 ns —
Maximum Operating Frequency [DATA_NEEDED: fMAX value] —
Supply Voltage VCCINT 3.3 V —
MultiVolt I/O Voltage 1.8 V / 2.5 V / 3.3 V / 5.0 V tolerant —
Process Technology 0.30 µm CMOS EEPROM —
Packhaging 256-ball FBGA (Fine-Pitch BGA), 17 mm × 17 mm, 1.0 mm pitch 256-ball FineLine BGA (FBGA-256)
In-System Programmability IEEE Std. 1532 compliant via JTAG —
Boundary-Scan Test IEEE Std. 1149.1 (JTAG) —
Operating Temperature (Industrial) -40 °C to +85 °C —
Tindminan RoHS [DATA_NEEDED: confirm from data] [DATA_NEEDED: RoHS status]
Uri ng Pagpapasok Surface Mount (BGA) Surface Mount
Pin-to-Pin Logic Delay — 7.5 ns
Counter Frequency (max) — 227.3 MHz
Supply Voltage - Core (VCCINT) — 3.0 V to 3.6 V (3.3 V typ.)
I/O Voltage (VCCIO) — 5.0 V / 3.3 V / 2.5 V (MultiVolt)
Programming — EEPROM, IEEE 1149.1 JTAG ISP (IEEE 1532-compliant)
Temperature na Operasyon — [DATA_NEEDED: operating temperature grade]
Configuration Memory — Non-volatile EEPROM

Mga Datasheets at Resources

Tingnan ang Lahat ng mga Produkto Lumikha ng BOM Hilingin ang Kita