EPM3512AQC208-3 vs EPM3512AQC208-10N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM3512AQC208-3 sa pamamagitan ng Altera at EPM3512AQC208-10N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM3512AQC208-3 EPM3512AQC208-10N
Brand Altera Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Huling Pagbili Obsolete
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Macrocells 512 512
Logic Array Blocks (LABs) 16 (32 macrocells each) 16
Maximum User I/O Pins 172 —
Packhaging PQFP-208 208-pin PQFP (Plastic Quad Flat Pack)
Speed Grade -3 -10
Supply Voltage - Core (VCCINT) 3.3 V —
I/O Bank Supply Voltage (VCCIO) 2.5 V / 3.3 V / 5.0 V (multiVolt) —
In-System Programmability Yes (IEEE Std. 1532 compliant) —
Boundary-Scan Test Yes (IEEE Std. 1149.1 / JTAG) —
Program/Erase Cycles 100 minimum [DATA_NEEDED: exact datasheet figure] —
Non-Volatile Configuration Yes (EEPROM-based) —
Temperature na Operasyon [DATA_NEEDED: industrial/commercial grade range] 0 C to 70 C (commercial)
Tindminan RoHS [DATA_NEEDED: confirm from datasheet] [DATA_NEEDED: RoHS status not in verified web data]
Uri ng Pagpapasok Surface Mount —
Level ng MSL [DATA_NEEDED: moisture sensitivity level] —
Usable Gates — Up to 10,000
User I/Os — 172
Volte ng Pagbibigay — 3.3 V
Pin-to-Pin Delay — 4.5 ns (-10 speed grade)
Maximum Internal Frequency — 227.3 MHz
Process Technology — CMOS EEPROM
In-System Programming — IEEE Std. 1149.1 JTAG, IEEE Std. 1532
Boundary-Scan Test (BST) — Built-in, IEEE 1149.1 compliant
I/O Standards — MultiVolt (1.8V / 2.5V / 3.3V)

Mga Datasheets at Resources

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