EPM5032DC-15 vs EPM5032DC-25 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5032DC-15 sa pamamagitan ng Altera at EPM5032DC-25 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPM5032DC-15 - 600-Gate, 32-Macrocell UV PLD | Altera MAX 5000 | DIP-28
EPM5032DC-15 ObsoletePagsanggunian na paghahambing
| Parametro | EPM5032DC-15 | EPM5032DC-25 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Family | MAX 5000 | — |
| Device Type | UV-erasable EPLD (PAL-type CMOS) | UV Erasable Programmable Logic Device (EPLD) |
| Usable Gates | 600 | — |
| Macrocells | 32 | 32 |
| Propagation Delay (tPD) | 15 ns | — |
| Maximum Toggle Frequency (fMAX) | 83.3 MHz | — |
| Supply Voltage (VCC) | 5 V (nominal) | — |
| Logic Family | CMOS, TTL-compatible I/O | — |
| Programmable Pins | 16 bidirectional I/O + 4 dedicated input = 20 | — |
| Total Package Pins | 28 | — |
| Packhaging | CERDIP-28 (windowed, through-hole) | CDIP-28 (Windowed Ceramic DIP-28) |
| Uri ng Pagpapasok | Through-Hole (DIP) | — |
| Temperature na Operasyon | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature range] |
| Erasure Method | UV light through ceramic quartz window | UV light through ceramic window |
| Process Technology | CMOS | CMOS, EPROM (UV-Erasable) |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | Lead Free / RoHS Compliant (per distributor listings) |
| Lead-Free | unknown | — |
| Manufacturer | — | Altera (Intel Programmable Solutions Group) |
| Product Family | — | MAX 5000 |
| Pin-to-Pin Propagation Delay (tPD) | — | 25 ns |
| Maximum Counter Frequency (fCNT) | — | [DATA_NEEDED: maximum counter frequency] |
| Setup Time (tSU) | — | [DATA_NEEDED: setup time] |
| Number of Dedicated Inputs | — | 32 (in DIP-28 pinout) |
| Number of I/O Pins | — | 22 (in DIP-28 pinout, 4 used as dedicated inputs) |
| Architecture | — | PAL-Type, Single-LAB, 32-Macrocell |
| Output Structure | — | Programmable I/O with output enable |
| Flip-Flop Configuration | — | D, T, JK, or SR (programmable) |
| Programming Method | — | UV erase + Altera/Intel MAX+PLUS II programmer |