EPM5032DI-20 vs EPM5032DM Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5032DI-20 sa pamamagitan ng Intel at EPM5032DM sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5032DI-20 | EPM5032DM |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | MAX 5000 (Altera legacy EPLD) | — |
| Architecture | CMOS PAL-type EPLD with PIA | — |
| Macrocells | 32 | 32 |
| Dedicated Inputs | 7 | — |
| Bidirectional I/O Pins | 16 | — |
| Product Terms | 320 (maximum) | — |
| Flip-Flops | 16 (one per macrocell) | — |
| Maksimum na Taktiko ng Oras | 62.5 MHz | — |
| Pin-to-Pin Delay | 20 ns (speed grade -20) | — |
| Packhaging | Ceramic DIP-20 (windowed, UV-erasable) | CDIP-28 (ceramic windowed DIP, 28-pin) |
| Temperature na Operasyon | Industrial (per 'I' suffix) | -55C to +125C (military/extended, ceramic package) |
| Programming | UV-erasable CMOS, JEDEC fuse file | — |
| Development Tool | Altera MAX+PLUS II (legacy) | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance status for ceramic DIP variant] | Non-compliant (ceramic DIP with UV window) |
| Lead-Free | [DATA_NEEDED: lead-free status] | No (ceramic DIP contains lead) |
| Device Family | — | MAX 5000 |
| Propagation Delay (tPD) | — | 25 ns |
| Usable Gates | — | 600 to 1000 (typical) |
| Logic Inputs | — | 32 |
| Process Technology | — | CMOS EEPROM |
| Supply Voltage (VCC) | — | 5 V (typical) |
| Standby Current | — | [DATA_NEEDED: ICC standby current] |
| Programming Technology | — | UV-erasable (windowed) EEPROM |
| Logic Function | — | Combinational and registered (synchronous) |
| Output Polarity | — | Programmable |
| Program Retention | — | Non-volatile (EEPROM) |
| Uri ng Pagpapasok | — | Through-hole (DIP) |