EPM5032DI-25 vs EPM5032DI-20 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM5032DI-25 sa pamamagitan ng Altera at EPM5032DI-20 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM5032DI-25 EPM5032DI-20
Brand Altera Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND Obsolete
Family MAX 5000 MAX 5000 (Altera legacy EPLD)
Device Type UV-erasable Programmable Logic Device (PLD) —
Architecture PAL-type, CMOS, AND-OR sum-of-products CMOS PAL-type EPLD with PIA
Macrocells 32 32
Product Terms 320 320 (maximum)
Logic Gates [DATA_NEEDED: equivalent gate count] —
Dedicated Inputs 7 7
Bidirectional I/O Pins 16 16
Total Array Inputs 24 —
Registered Outputs 16 —
Global Clocks 1 —
Propagation Delay (tPD) 25 ns —
Maximum Clock Frequency (fMAX) 62.5 MHz —
Volte ng Pagbibigay 5 V —
Process Technology CMOS —
Packhaging Ceramic DIP, windowed (UV-erasable) Ceramic DIP-20 (windowed, UV-erasable)
Bilang ng Pin [DATA_NEEDED: exact pin count - 24 or 28] —
Temperature na Operasyon 0C to +70C (commercial) Industrial (per 'I' suffix)
I/O Standard TTL-compatible —
Programmability UV-erasable, EPROM-based —
Development Tool MAX+PLUS II / A+PLUS Altera MAX+PLUS II (legacy)
Tindminan RoHS [DATA_NEEDED: likely non-compliant due to ceramic DIP] [DATA_NEEDED: RoHS compliance status for ceramic DIP variant]
Lifecycle Not Recommended for New Designs (NRND) —
Flip-Flops — 16 (one per macrocell)
Maksimum na Taktiko ng Oras — 62.5 MHz
Pin-to-Pin Delay — 20 ns (speed grade -20)
Programming — UV-erasable CMOS, JEDEC fuse file
Lead-Free — [DATA_NEEDED: lead-free status]

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