EPM5032JC25 vs EPM5064JC Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM5032JC25 sa pamamagitan ng Altera at EPM5064JC sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM5032JC25 EPM5064JC
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family MAX 5000 MAX 5000
Device EPM5032 —
Logic Elements 32 macrocells —
Propagation Delay (tPD) 25 ns —
Maximum Internal Frequency 62.5 MHz —
Product Terms 320 —
Flip-Flops 32 —
Dedicated Inputs 7 —
Bidirectional I/O Pins 16 —
Total Inputs to Array 24 —
Bilang ng Outputs 16 —
Architecture PAL-type macrocells with global Programmable Interconnect Array (PIA) —
Technology CMOS EPROM, UV-erasable (windowed) / OTP —
Volte ng Pagbibigay 5 V (TTL-level I/O) —
Packhaging 28-pin PLCC (JC) 68-pin PLCC (JEDEC)
Uri ng Pagpapasok Surface Mount Surface Mount (socketed)
Tindminan RoHS [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS compliance]
Device Type — EPLD (Erasable PLD)
Macrocells — 64
Usable Gates — 1,250 (approx.)
Logic Array Inputs — 36
Logic Array Outputs — 64
Supply Voltage (VCC) — 5 V (typical, 4.75 V - 5.25 V range)
I/O Logic Level — TTL / CMOS compatible
Configuration Memory — EPROM (UV-erasable window or OTP)
Temperature na Operasyon — [DATA_NEEDED: operating temperature grade]
Pin-to-Pin Delay (tPD) — [DATA_NEEDED: specific tPD grade value]
Maximum Frequency (fMAX) — [DATA_NEEDED: fCNT grade value]
Lead-Free — [DATA_NEEDED: lead-free status]
Level ng MSL — [DATA_NEEDED: MSL rating]
Programming Tool — Altera MAX+PLUS II / Quartus II (legacy device support)

Mga Datasheets at Resources

Tingnan ang Lahat ng mga Produkto Lumikha ng BOM Hilingin ang Kita