EPM5032LC-20 vs EPM5032LC-25 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM5032LC-20 sa pamamagitan ng Altera at EPM5032LC-25 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM5032LC-20 EPM5032LC-25
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete NRND
Device Family MAX 5000 MAX 5000
Product Type EPLD / CPLD (One-Time Programmable / UV-Erasable) —
Usable Gates 600 gates —
Macrocells 32 32
Logic Blocks (LABs) 1 —
Speed Grade -20 (20 ns pin-to-pin) —
Maximum Frequency 71.4 MHz —
Propagation Delay (tPD) 20 ns 25 ns
Supply Voltage (VCC) 5 V ±5% 5 V ±10% (4.5 V to 5.5 V)
Temperature na Operasyon 0 °C to +70 °C (commercial; -55 °C to +125 °C military per /883B variants) 0 °C to +70 °C (commercial, "LC" suffix)
Dedicated Inputs 7 7
Bidirectional I/O Pins 16 —
Total Inputs 24 24 (7 dedicated + 16 I/O used as input)
Output Functions 16 —
Product Terms per Output 16 —
Programmable Interconnect Programmable Interconnect Array (PIA) —
Packhaging LCC-28 (Plastic Leaded Chip Carrier, J-lead) 28-pin PLCC (JEDEC S-PQCC-J28), 1.27 mm pitch
Uri ng Pagpapasok Surface Mount Surface Mount, socket-compatible
Tindminan RoHS [DATA_NEEDED: RoHS status] Not RoHS compliant (legacy Altera product)
Level ng MSL [DATA_NEEDED: MSL] —
Architecture — PAL-type EPLD (Erasable Programmable Logic Device)
Technology — CMOS, UV-erasable / OTP
Product Terms — 320
I/O Pins — 16 bidirectional
Maximum Internal Frequency — 62.5 MHz
I/O Standard — 5 V CMOS
Configuration Cell — Programmable interconnect array (PIA), OTP / UV-erasable

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