EPM5064JC vs EPM5064JI-1 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM5064JC sa pamamagitan ng Altera at EPM5064JI-1 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM5064JC EPM5064JI-1
Brand Altera Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete NRND
Family MAX 5000 MAX 5000
Device Type EPLD (Erasable PLD) EPLD (Erasable Programmable Logic Device)
Macrocells 64 64
Usable Gates 1,250 (approx.) —
Logic Array Inputs 36 —
Logic Array Outputs 64 —
Packhaging 68-pin PLCC (JEDEC) 68-pin PLCC (windowed ceramic)
Uri ng Pagpapasok Surface Mount (socketed) Surface Mount
Supply Voltage (VCC) 5 V (typical, 4.75 V - 5.25 V range) —
I/O Logic Level TTL / CMOS compatible —
Configuration Memory EPROM (UV-erasable window or OTP) —
Temperature na Operasyon [DATA_NEEDED: operating temperature grade] [DATA_NEEDED: commercial vs industrial grade temp range]
Pin-to-Pin Delay (tPD) [DATA_NEEDED: specific tPD grade value] —
Maximum Frequency (fMAX) [DATA_NEEDED: fCNT grade value] —
Tindminan RoHS [DATA_NEEDED: RoHS compliance] [DATA_NEEDED: not stated in provided data]
Lead-Free [DATA_NEEDED: lead-free status] —
Level ng MSL [DATA_NEEDED: MSL rating] —
Programming Tool Altera MAX+PLUS II / Quartus II (legacy device support) —
User I/O Pins — [DATA_NEEDED: user I/O count from datasheet]
Logic Elements — [DATA_NEEDED: total logic elements]
Propagation Delay (tPD) — [DATA_NEEDED: combinational tPD from datasheet]
Volte ng Pagbibigay — 5 V
Process Technology — CMOS, UV-erasable
Speed Grade — JI-1 (commercial, -10/-12/-15 family)
Programmability — UV-erasable (windowed package)
Data Retention — 25 years (per MAX 5000 datasheet)

Mga Datasheets at Resources

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