EPM5064LC-1 vs EPM5064JC Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM5064LC-1 sa pamamagitan ng Altera at EPM5064JC sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM5064LC-1 EPM5064JC
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Product Type CPLD (Complex Programmable Logic Device) —
Family MAX 5000 MAX 5000
Macrocells 64 64
Logic Array Blocks (LABs) 4 —
Usable Gates 1.25K (approx.) 1,250 (approx.)
Supply Voltage (VCC) 4.75 V to 5.25 V 5 V (typical, 4.75 V - 5.25 V range)
Internal Operating Frequency 62.5 MHz —
Propagation Delay (tPD) 40 ns —
Input Lines 36 —
Dedicated Inputs 7 —
Output Lines 28 —
Programming Technology OTP / UV-Erasable EPROM —
Packhaging 44-pin PLCC (Plastic Leaded Chip Carrier) 68-pin PLCC (JEDEC)
Process Technology CMOS —
Temperature na Operasyon [DATA_NEEDED: operating temperature range] [DATA_NEEDED: operating temperature grade]
Tindminan RoHS [DATA_NEEDED: RoHS compliance] [DATA_NEEDED: RoHS compliance]
Programming Interface JTAG (ByteBlaster-compatible) —
Device Type — EPLD (Erasable PLD)
Logic Array Inputs — 36
Logic Array Outputs — 64
Uri ng Pagpapasok — Surface Mount (socketed)
I/O Logic Level — TTL / CMOS compatible
Configuration Memory — EPROM (UV-erasable window or OTP)
Pin-to-Pin Delay (tPD) — [DATA_NEEDED: specific tPD grade value]
Maximum Frequency (fMAX) — [DATA_NEEDED: fCNT grade value]
Lead-Free — [DATA_NEEDED: lead-free status]
Level ng MSL — [DATA_NEEDED: MSL rating]
Programming Tool — Altera MAX+PLUS II / Quartus II (legacy device support)

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