EPM5064LC vs EPM5064LC-2 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM5064LC sa pamamagitan ng Altera at EPM5064LC-2 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM5064LC EPM5064LC-2
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family MAX 5000 —
Device Type CPLD (Complex Programmable Logic Device) —
Programming Type OTP (One-Time-Programmable, UV-erasable EPROM) —
Macro Cells 64 —
Usable Gates 1.25K —
Logic Array Blocks (LABs) 4 4
Propagation Delay (tPD) 55 ns 45 ns
Total Inputs 36 (7 dedicated + 29 I/O) —
I/O Pins 28 bidirectional + 4 dedicated input —
Supply Voltage (VCC) 4.75 V to 5.25 V 4.75 V to 5.25 V (5 V nominal)
Temperature na Operasyon 0C to +70C (Commercial) -40 C to +85 C (commercial LC grade) [DATA_NEEDED: explicit min/max in source]
Packhaging PLCC-44 (LCC-44, J-lead) PLCC-44 (J-Lead, plastic)
Process Technology CMOS EPROM CMOS, OTP EPROM (UV-erasable base)
Uri ng Pagpapasok Surface Mount Surface Mount
Tindminan RoHS [DATA_NEEDED: RoHS status - pre-RoHS legacy part, likely non_compliant] [DATA_NEEDED: not specified in source]
Lead Free [DATA_NEEDED: lead-free status] —
Device Family — MAX 5000
Product Type — CPLD (Complex Programmable Logic Device)
Macrocells — 64
Logic Elements per LAB — 16
Number of Inputs — 36 (7 dedicated + 28 I/O)
Number of I/O Pins — 28
Number of Flip-Flops — 28
Maximum Internal Frequency — 40 MHz
Programmable Polarity — Yes
Programmable Output Enable — Yes, per macrocell
Programming Method — Altera byte-wide / JTAG programmer

Mga Datasheets at Resources

Tingnan ang Lahat ng mga Produkto Lumikha ng BOM Hilingin ang Kita