EPM5128GC vs EPM5128GC2 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM5128GC sa pamamagitan ng Altera at EPM5128GC2 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM5128GC EPM5128GC2
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family MAX 5000 MAX 5000
Macrocells 128 —
Usable Gates 2,500 2.5K
Logic Elements / LABs [DATA_NEEDED: LAB count] —
User I/Os 68 —
Package Type WPGA (Windowed Ceramic Pin Grid Array) —
Package Code WPGA —
Number of Terminals 68 —
Terminal Form PIN/PEG (through-hole PGA with alignment pegs) —
Package Shape Square —
Temperature Grade Commercial —
Supply Voltage (Vcc) 5 V —
Process Technology CMOS, UV-erasable CMOS EPROM
Architecture EPLD, programmable AND/OR array with fixed OR plane AND/OR plane + programmable macro cell + PIA
Propagation Delay (tpd) [DATA_NEEDED: tpd in ns] —
Maximum Frequency (fmax) [DATA_NEEDED: fmax in MHz] —
Programmable Security Bit Yes —
Configuration Memory Non-volatile UV-EPROM (windowed ceramic) On-chip EPROM (no external boot device)
Uri ng Pagpapasok Through-Hole (PGA socket required) —
Tindminan RoHS [DATA_NEEDED: RoHS compliance] [DATA_NEEDED: RoHS status]
Device Type — EPLD (Erasable Programmable Logic Device)
Macro Cells — 128
Logic Array Blocks (LABs) — 8 (16 macro cells each)
Maximum Internal Frequency — 50 MHz
Supply Voltage VCC — 5 V
I/O Pins — 64
Dedicated Inputs — 16
Packhaging — Ceramic PGA (GC, windowed)
Programmable Flip-Flop Modes — D / T / JK / SR (selectable)
Reprogrammability — UV-erasable (windowed ceramic package)
Temperature na Operasyon — [DATA_NEEDED: operating temperature range]
Bilang ng Pin — [DATA_NEEDED: total PGA pin count]

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