EPM5128JC-2 vs EPM5128GC-1 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM5128JC-2 sa pamamagitan ng Altera at EPM5128GC-1 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM5128JC-2 EPM5128GC-1
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family MAX 5000 MAX 5000
Device Type UV-Erasable Programmable Logic Device (PLD) UV-erasable CMOS CPLD
Macrocells 128 128
Dedicated Inputs 7 7
Propagation Delay (tPD) 45 ns (max) 16 ns (typical, -1 speed grade)
Maximum Counter Frequency (fCNT) 50 MHz —
Input Setup Time (tSU) 7.5 ns —
Output Drive Current (IOH/IOL) 12 mA DC —
Process Technology CMOS —
Packhaging 68-pin CQCC (Ceramic Quad Flat Pack), windowed PGA-96+ (Pin Grid Array, ceramic windowed)
Uri ng Pagpapasok Surface Mount —
Temperature na Operasyon [DATA_NEEDED: operating temperature range] -40C to +85C (industrial)
Volte ng Pagbibigay 5 V (nominal) —
Program/Erase Method UV (ceramic window) —
Erase/Program Cycles [DATA_NEEDED: minimum erase/program cycles] —
Tindminan RoHS Non-compliant (ceramic windowed package contains lead-bearing solder) [DATA_NEEDED: RoHS compliance - ceramic PGA part is legacy]
Logic Family TTL-compatible I/O —
Usable Gates — 2,500
Maximum User I/O Pins — 52
Nominal Supply Voltage — 5 V
Supply Voltage Range — 4.75 V to 5.25 V
Maximum Operating Frequency — 62.5 MHz
Technology — CMOS, UV-erasable EPROM
IOL / IOH — 100 mA / 25 mA per pin (legacy figure, [DATA_NEEDED: verify exact drive spec])
Security Bit — Programmable, prevents readback
Programming Method — UV erase + EPROM program (or device programmer)
Level ng MSL — [DATA_NEEDED: MSL level]

Mga Datasheets at Resources

Tingnan ang Lahat ng mga Produkto Lumikha ng BOM Hilingin ang Kita