EPM5128JC-2 vs EPM5128JC Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM5128JC-2 sa pamamagitan ng Altera at EPM5128JC sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM5128JC-2 EPM5128JC
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family MAX 5000 —
Device Type UV-Erasable Programmable Logic Device (PLD) EPLD / CPLD
Macrocells 128 —
Dedicated Inputs 7 8
Propagation Delay (tPD) 45 ns (max) 35 ns
Maximum Counter Frequency (fCNT) 50 MHz —
Input Setup Time (tSU) 7.5 ns —
Output Drive Current (IOH/IOL) 12 mA DC —
Process Technology CMOS CMOS EPROM
Packhaging 68-pin CQCC (Ceramic Quad Flat Pack), windowed —
Uri ng Pagpapasok Surface Mount Surface Mount (PLCC socket or solder)
Temperature na Operasyon [DATA_NEEDED: operating temperature range] Commercial 0C to +70C
Volte ng Pagbibigay 5 V (nominal) —
Program/Erase Method UV (ceramic window) —
Erase/Program Cycles [DATA_NEEDED: minimum erase/program cycles] —
Tindminan RoHS Non-compliant (ceramic windowed package contains lead-bearing solder) [DATA_NEEDED: RoHS status - legacy part]
Logic Family TTL-compatible I/O —
Product Family — MAX 5000
Macrocell Count — 128
Logic Elements — Programmable AND/OR/XOR array
Supply Voltage (VCC) — 5 V (typical)
Bilang ng Pins — 68
Package Type — PLCC-68 (JLCC) ceramic, J-leaded
User I/O Pins — [DATA_NEEDED: user I/O pin count]
Configuration Memory — UV-erasable EPROM (windowed package)
Programming Interface — Altera MAX+PLUS II / A+PLUS / legacy programmer
Boundary Scan — JTAG IEEE 1149.1 (family feature)
Lead-Free — [DATA_NEEDED: lead-free status]

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