EPM5130JI vs EPM5130GI Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5130JI sa pamamagitan ng Altera at EPM5130GI sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5130JI | EPM5130GI |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | MAX 5000 | — |
| Device Type | UV-Erasable EPLD (CMOS EPROM) | — |
| Macrocells | 128 | 128 |
| Logic Array Blocks (LABs) | 8 | 8 |
| Maksimum na Taktiko ng Oras | 33.3 MHz | — |
| Propagation Delay (tPD) | 55 ns | 55 ns |
| External Clock Inputs | 1 (shared input/clock) | — |
| Interconnect | Programmable Interconnect Array (PIA) | Programmable Interconnect Array (PIA) |
| Process Technology | 0.75 micron CMOS EPROM | CMOS |
| Volte ng Pagbibigay | 5 V (typical) | 5 V |
| Input Logic Standard | TTL-compatible | — |
| Package Type | Ceramic J-Leaded Chip Carrier (JLCC) with UV window | — |
| Temperature na Operasyon | Commercial (0C to +70C) | -40C to +85C (industrial) |
| Program/Erase Method | UV erasure through quartz window | — |
| Tindminan RoHS | Non-compliant (contains Pb in ceramic package) | [DATA_NEEDED: RoHS status] |
| Lifecycle | Obsolete - EOL by Altera/Intel | — |
| Device Family | — | MAX 5000 |
| Architecture | — | EPLD (Erasable Programmable Logic Device), UV-erasable |
| Dedicated Inputs | — | 19 |
| Total Inputs | — | 68 |
| I/O Pins | — | 48 |
| Maximum Clock Frequency (fMAX) | — | 33.3 MHz |
| External Clock Pins | — | 1 |
| Packhaging | — | Ceramic Pin Grid Array (PGA), windowed |
| Programming Method | — | UV erasure + EPROM programming |