EPM5130WC-1AA vs EPM5130WC-2 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM5130WC-1AA sa pamamagitan ng Altera at EPM5130WC-2 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM5130WC-1AA EPM5130WC-2
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Device Family MAX 5000 MAX 5000
Macrocell Count 128 128
Number of Logic Array Blocks 8 (typical for MAX 5130) —
Propagation Delay (tPD, max) 40 ns —
Maximum Toggle Frequency (fCNT) 50 MHz —
Maximum Clock Frequency (fMAX) [DATA_NEEDED: fMAX exact value] —
Dedicated Inputs 19 19
I/O Pins 48 —
Total Inputs (incl. I/O feedback) 68 —
Total Outputs 48 —
Process Technology 5 V CMOS, UV-erasable CMOS
Packhaging Windowed Ceramic WQFP (AA suffix) —
Temperature na Operasyon [DATA_NEEDED: commercial or industrial temp grade] 0 °C to 70 °C (Commercial)
Supply Voltage (VCC) 5 V nominal 4.75 V to 5.25 V
Programming Method UV erase + EPROM programming —
Tindminan RoHS unknown (legacy package, likely non-compliant) [DATA_NEEDED: RoHS status]
Logic-to-Pin Ratio Highest in-class per Altera marketing literature —
Product Type — UV-Erasable PLD (CPLD)
Propagation Delay (tPD) — 45 ns
User I/O Lines — 48
Total Inputs (I/O + dedicated) — 68
Package Type — 100-terminal Ceramic CQFP (R-CQFP-G100), windowed, gull-wing
Terminal Pitch — 0.650 mm
Uri ng Pagpapasok — Surface Mount
Configuration Memory — UV-erasable CMOS EEPROM cells
Speed Grade — -2 (45 ns)
Lead-Free — [DATA_NEEDED: lead-free status]
Logic Elements — AND/OR array with programmable macrocell register

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