EPM5192AGC84-20 vs EPM5192AGC-15 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM5192AGC84-20 sa pamamagitan ng Altera at EPM5192AGC-15 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM5192AGC84-20 EPM5192AGC-15
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Product Type Complex Programmable Logic Device (CPLD) EPLD (Erasable Programmable Logic Device)
Family MAX 5000 —
Macrocells 192 192
User I/O Pins 64 —
Dedicated Inputs 7 7
Logic Gates (typical) [DATA_NEEDED: typical gate count] —
Maximum Clock Frequency (fMAX) 66.7 MHz —
Pin-to-Pin Delay (tPD) 20 ns —
Speed Grade -20 —
Packhaging 84-pin Ceramic Pin Grid Array (CPGA, WPGA) Ceramic Pin Grid Array (PGA)
Package Code WPGA —
Erasure Method UV-Erasable (with OTP window) —
Process Technology CMOS —
Operating Temperature Grade Commercial —
Volte ng Pagbibigay [DATA_NEEDED: VCC range] —
I/O Standard 5V CMOS / TTL compatible —
Tindminan RoHS [DATA_NEEDED: RoHS compliance] [DATA_NEEDED: RoHS status - legacy ceramic PGA typically non-compliant]
Uri ng Pagpapasok Through-Hole (Pin Grid Array socket) —
Series — MAX 5000
Logic Array Blocks — 16 (typical for 192-macrocell MAX 5000)
Maximum User I/O Pins — 64
Total Inputs — 72
Propagation Delay (tPD) — 15 ns (pin-to-pin, -15 speed grade)
Supply Voltage (VCC) — 5 V
Technology — CMOS, UV-erasable EPROM
Programming Method — UV erase + EPROM program (via Altera programmer)
Temperature na Operasyon — [DATA_NEEDED: operating temperature range]
Katayuan ng Lifecycle — Obsolete / Last Time Buy (per Altera legacy product list)

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