EPM5192AJC84-20 vs EPM5192AJM84-20 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5192AJC84-20 sa pamamagitan ng Altera at EPM5192AJM84-20 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPM5192AJC84-20 - 192-Macrocell UV PLD, 33ns, 84-Pin J-Lead | Altera
EPM5192AJC84-20 Obsolete
Pagsanggunian na paghahambing
| Parametro | EPM5192AJC84-20 | EPM5192AJM84-20 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | MAX 5000 | — |
| Device Type | UV-erasable/OTP Complex PLD (CPLD) | CMOS UV-Erasable/OTP Complex PLD |
| Macrocells | 192 | 192 |
| Propagation Delay (tpd) | 33 ns (speed grade -20) | — |
| Maksimum na Taktiko ng Oras | 66.7 MHz | 66.7 MHz |
| Supply Voltage (Vcc) | 4.75 V to 5.25 V | — |
| Dedicated Inputs | 7 | 7 |
| User I/O Lines | 64 | — |
| Process Technology | CMOS, UV-erasable EEPROM | CMOS EPROM (UV-erasable) |
| Packhaging | 84-pin PLCC J-Lead (WQCCJ, J84) | 84-pin CQFP (S-CQCC-J84, J-lead) |
| Operating Temperature Grade | Commercial | — |
| Uri ng Pagpapasok | Surface Mount (J-Lead) | — |
| Level ng MSL | [DATA_NEEDED: MSL level] | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: rohs status] |
| Programming Tool | Altera MAX+PLUS II / Quartus (legacy) | — |
| Lead-Free / Halogen-Free | [DATA_NEEDED: lead-free status] | — |
| Manufacturer | — | Altera (now Intel) |
| Series | — | MAX 5000 (EPM5192) |
| Logic Array Blocks (LABs) | — | 12 |
| User I/O Pins | — | 64 |
| Programmable Interconnect | — | PIA (Programmable Interconnect Array) |
| Propagation Delay (tPD) | — | 33 ns (speed grade -20) |
| Terminal Form | — | J-Bend |
| Temperature Grade | — | MILITARY |
| Erasure Method | — | UV (quartz-windowed CQFP) or OTP |